参数资料
型号: IDT74LVCH646APG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线收发器
英文描述: LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封装: TSSOP-24
文件页数: 6/7页
文件大小: 96K
代理商: IDT74LVCH646APG
6
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVCH646A
3.3V CMOS OCTAL BUS TRANSCEIVER AND REGISTER
Open
VLOAD
GN D
VCC
Pulse
Generator
D.U.T.
500
CL
RT
VIN
VOUT
(1, 2)
8L V C Link
IN PU T
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OU TPUT 1
OU TPUT 2
tPHL1
tSK (x)
tPLH2
tPHL2
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
8LV C Link
SAME PHASE
INPUT TR AN SITION
OPPOSITE PHASE
INPUT TR AN SITION
0V
VOH
VOL
tPLH
tPHL
tPLH
OU TPU T
VIH
VT
VIH
VT
8LV C Link
DATA
IN PU T
0V
tREM
TIMING
INPUT
ASYN C HRONO US
CONTRO L
SYN C HRONO US
CONTRO L
tSU
tH
tSU
tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
8LV C Link
LO W -HIGH-LOW
PULSE
HIG H-LOW -H IGH
PULSE
VT
tW
VT
8L V C Link
CONTRO L
IN PU T
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SW ITCH
CLO SE D
OUTPUT
NORMALLY
HIGH
EN ABLE
D ISABLE
SW ITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
tPZL
VLOAD/2
VIH
VT
VOL
VHZ
8LV C Link
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - tsk (x)
PULSE WIDTH
Symbol
VCC(1)= 3.3V ±0.3V
VCC(1) = 2.7V
VCC(2)= 2.5V ±0.2V Unit
VLOAD
66
2 x Vcc
V
VIH
2.7
Vcc
V
VT
1.5
VCC / 2
V
VLZ
300
150
mV
VHZ
300
150
mV
CL
50
30
pF
8LVC Link
DEFINITIONS:
CL=
Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other tests
Open
8LVC Link
相关PDF资料
PDF描述
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