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参数资料
| 型号： | IDT74FCT388915TEJG8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 6/10页 |
| 文件大小： | 119K |
| 代理商： | IDT74FCT388915TEJG8 |
COMMERCIALTEMPERATURERANGE
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
5
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Condition(1)
Min.
Max.
Unit
tRISE/FALL
Rise/Fall Time
Load = 50
Ω to VCC/2, CL = 20pF
0.2(2)
2ns
All Outputs
(between 0.8V and 2V)
tPULSEWIDTH(3)
Output Pulse Width
Load = 50
Ω to VCC/2, CL = 20pF
0.5tCYCLE –0.8(5) 0.5tCYCLE+ 0.8(5)
ns
Q,
Q, Q/2 outputs(3)
Q0-Q4,
Q5, Q/2, @ 1.5V
tPULSEWIDTH
Output Pulse Width
0.5tCYCLE–1(5)
0.5tCYCLE+ 1(5)
ns
2QOutput(3)
2Q @ 1.5V
tPD
SYNC input to FEEDBACK delay
Load = 50
Ω to VCC/2, CL = 20pF
+0.1
+1.3
ns
SYNC-FEEDBACK(3) (measured at SYNC0 or 1 and FEEDBACK input pins)
0.1F from LF to Analog GND(5)
tSKEWr
Output to Output Skew between outputs 2Q, Q0-Q4,
Load = 50
Ω to VCC/2, CL = 20pF
—
600
ps
(rising)(3,4)
Q/2 (rising edges only)
tSKEWf
Output to Output Skew
—
250
ps
(falling)(3,4)
between outputs Q0-Q4 (falling edges only)
tSKEWall(3,4)
Output to Output Skew
—
800
ps
2Q, Q/2, Q0-Q4 rising,
Q5 falling
tLOCK(6)
Time required to acquire Phase-Lock from time
1(2)
10
ms
SYNC input signal is received
tPZH
OutputEnableTime
3(2)
14
ns
tPZL
OE/
RST (LOW-to-HIGH) to Q, 2Q, Q/2, Q
tPHZ
OutputDisableTime
3(2)
14
ns
tPLZ
OE/
RST (HIGH-to-LOW) to Q, 2Q, Q/2, Q
GENERAL AC SPECIFICATION NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested.
3. These specifications are guaranteed but not production tested.
4. Under equally loaded conditions, as specified under test conditions and at a fixed temperature and voltage.
5. tCYCLE = 1/frequency at which each output (Q,
Q, Q/2 or 2Q) is expected to run.
6. With VCC fully powered-on and an output properly connected to the FEEDBACK pin, tLOCK Max. is with C1 = 0.1F, tLOCK Min. is with C1 = 0.01F. (Where C1 is loop filter
capacitor shown in Figure 2).
7. The wiring diagrams and written explanations of Figure 3 demonstrate the input and output frequency relationships for various possible feedback configurations. The allowable
SYNC input range to stay in the phase-locked condition is also indicated. There are two allowable SYNC frequency ranges, depending on whether FREQ_SEL is HIGH or LOW.
Also it is possible to feed back the
Q5 output, thus creating a 180° phase shift between the SYNC input and the Q outputs. The table below summarizes the allowable SYNC
frequency range for each possible configuration.
FREQ_SEL
Feedback
Allowable SYNC Input
Corresponding 2Q Output
Phase Relationship of the Q Outputs
Level
Output
Frequency Range (MHZ)
Frequency Range
to Rising SYNC Edge
HIGH
Q/2
10 to (2x_Q fMAX Spec)/4
40 to (2Q fMAX Spec)
0°
HIGH
Any Q (Q0-Q4)
20 to (2x_Q fMAX Spec)/2
40 to (2Q fMAX Spec)
0°
HIGH
Q5
20 to (2x_Q fMAX Spec)/2
40 to (2Q fMAX Spec)
180°
HIGH
2X_Q
40 to (2x_Q fMAX Spec)
40 to (2Q fMAX Spec)
0°
LOW
Q/2
5 to (2x_Q fMAX Spec)/8
20 to (2Q fMAX Spec)/2
0°
LOW
Any Q (Q0-Q4)
10 to (2x_Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
0°
LOW
Q5
10 to (2x_Q fMAX Spec)/4
20 to (2Q fMAX Spec)/2
180°
LOW
2X_Q
20 to (2x_Q fMAX Spec)/2
20 to (2Q fMAX Spec)/2
0°
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| IDT74FCT399P | 制造商:Integrated Device Technology Inc 功能描述: |
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| IDT74FCT521ATPYG | 功能描述:IC COMPARATOR IDENTITY 8B 20SSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 比较器 系列:74FCT 标准包装:1 系列:4000B 类型:幅值比较器 位数:4 输出:高有效 输出功能:A<B，A=B，A>B 电源电压:3 V ~ 18 V 输出电流高，低:4.2mA，4.2mA 额定电压和最大 CL 时的最大传播延迟:350ns @ 15V，50pF 电流 - 静态:100µA 工作温度:-55°C ~ 125°C 封装/外壳:16-SOIC（0.209"，5.30mm 宽） 安装类型:表面贴装 包装:剪切带 (CT) 其它名称:296-14121-1 |
| IDT74FCT521ATPYG8 | 功能描述:IC COMPARATOR IDENTITY 8B 20SSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 比较器 系列:74FCT 标准包装:1 系列:4000B 类型:幅值比较器 位数:4 输出:高有效 输出功能:A<B，A=B，A>B 电源电压:3 V ~ 18 V 输出电流高，低:4.2mA，4.2mA 额定电压和最大 CL 时的最大传播延迟:350ns @ 15V，50pF 电流 - 静态:100µA 工作温度:-55°C ~ 125°C 封装/外壳:16-SOIC（0.209"，5.30mm 宽） 安装类型:表面贴装 包装:剪切带 (CT) 其它名称:296-14121-1 |
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