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| 型号： | IDT74LVC109APG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | TSSOP-16 |
| 文件页数： | 1/6页 |
| 文件大小： | 80K |
| 代理商： | IDT74LVC109APG |
INDUSTRIALTEMPERATURERANGE
IDT74LVC109A
3.3V CMOS DUAL J-
K FLIP-FLOP WITH SET AND RESET
1
AUGUST 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4744/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in QSOP, SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVC109A
DESCRIPTION:
The LVC109A dual J-K flip-flop with set and reset, positive-edge trigger
is built using advanced dual metal CMOS technology. This device features
individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also
complementary Q and Qoutputs.Thesetandresetareasynchronousactive
low inputs and operate independently of the clock input. The J and K inputs
control the state changes of the flip-flops as described in the function table.
TheJandKinputsmustbestableonesetuptimepriortothelow-to-highclock
transition for predictable operation. The J-K design allows operation as a
D-type flip-flop by tying the J and K inputs together.
Inputs can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC109A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
3.3V CMOS DUAL
J-K FLIP-FLOP WITH SET AND
RESET, POSITIVE-EDGE TRIG-
GER, AND 5 VOLT TOLERANT I/O
C
K
J
SD
RD
CP
C
Q
3
2
5
1
4
7
6
NOTE:
Pin numbers are for section 1. Refer to pin configuration for section 2 pin numbers.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT74LVC112APY | 制造商:Integrated Device Technology Inc 功能描述:Flip Flop, Dual, J/K Type, 16 Pin, Plastic, SSOP |
| IDT74LVC138ADC | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APAG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:2,000 系列:74LVCH 逻辑类型:缓冲器/线路驱动器，非反相 元件数:2 每个元件的位元数:4 输出电流高，低:24mA，24mA 电源电压:1.65 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:20-SOIC（0.295"，7.50mm 宽） 供应商设备封装:20-SOIC 包装:带卷 (TR) |
| IDT74LVC162244APAG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:47 系列:74LVX 逻辑类型:缓冲器/线路驱动器，非反相 元件数:4 每个元件的位元数:1 输出电流高，低:4mA，4mA 电源电压:2 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-SOIC（0.209"，5.30mm 宽） 供应商设备封装:14-SOIC 包装:管件 |
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