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参数资料
| 型号： | IDT74LVC109APG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | TSSOP-16 |
| 文件页数： | 2/6页 |
| 文件大小： | 80K |
| 代理商： | IDT74LVC109APG |
INDUSTRIALTEMPERATURERANGE
2
IDT74LVC109A
3.3V CMOS DUAL J-
K FLIP-FLOP WITH SET AND RESET
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
–50
mA
IOK
VI < 0 or VO < 0
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
QSOP/ SOIC/ SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
PIN DESCRIPTION
Pin Names
Description
xCP
Clock Inputs, LOW-to-HIGH, edge-triggered
xRD
Asynchronous Reset Input (Active LOW)
xSD
Asynchronous Set Inputs (Active LOW)
xJ, xK
Synchronous Inputs
xQ
TrueFlip-FlopOutputs
xQ
ComplementFlip-FlopOutputs
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
VCC
1
RD
1
J
1
K
1
SD
1
Q
1
Q
GND
2
K
2
J
2
Q
1
CP
2
Q
2
CP
2
SD
2
RD
FUNCTIONAL DIAGRAM
1
RD
1
K
1SD
2
K
2
J
1
CP
Q
2
Q
2
CP
2
SD
2
RD
5
2
4
3
1
11
14
12
13
15
6
7
10
9
J
Q
RD
K
CP FF2
2
Q
SD
RD
Q
CP
SD
Q
J
K
1
Q
1
Q
1
J
FF1
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