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参数资料
| 型号： | IDT74LVC109AQ8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 锁存器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封装： | QSOP-16 |
| 文件页数： | 5/6页 |
| 文件大小： | 80K |
| 代理商： | IDT74LVC109AQ8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVC109A
3.3V CMOS DUAL J-
K FLIP-FLOP WITH SET AND RESET
5
Open
VLOAD
GND
VCC
Pulse
Generator
D.U.T.
500
500
CL
RT
VIN
VOUT
(1, 2)
LVC QUAD Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2
tPHL2
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC QUAD Link
DATA
INPUT
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU
tH
tSU
tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
VT
tW
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
VOH
VOL
tPLH
tPHL
tPLH
OUTPUT
VT
VIH
VT
VIH
VT
CONTROL
INPUT
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
tPHZ
0V
VLZ
VOH
VT
tPZL
VLOAD/2
VIH
VT
VOL
VHZ
LVC QUAD Link
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuit for All Outputs
Set-up, Hold, and Release Times
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
Output Skew - tSK(X)
Pulse Width
Symbol
VCC(1)=2.5V±0.2V
VCC(2)= 3.3V±0.3V & 2.7V
Unit
VLOAD
2 x Vcc
6
V
VIH
Vcc
2.7
V
VT
Vcc / 2
1.5
V
VLZ
150
300
mV
VHZ
150
300
mV
CL
30
50
pF
TEST CONDITIONS
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
VLOAD
Enable Low
Disable High
GND
Enable High
All Other Tests
Open
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
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