- 您现在的位置：买卖IC网 > PDF目录65591 > IDT74LVC16952APA8 (INTEGRATED DEVICE TECHNOLOGY INC) LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 PDF资料下载
参数资料
| 型号： | IDT74LVC16952APA8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封装： | 0.50 MM PITCH, TSSOP-56 |
| 文件页数： | 5/6页 |
| 文件大小： | 127K |
| 代理商： | IDT74LVC16952APA8 |
5
EXTENDEDCOMMERCIALTEMPERATURERANGE
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
Open
VLOAD
GND
VCC
Pulse
Generator
D.U.T.
500
500
CL
RT
VIN
VOUT
(1, 2)
LVC Link
INPUT
VIH
0V
VOH
VOL
tPLH1
tSK (x)
OUTPUT 1
OUTPUT 2
tPHL1
tSK (x)
tPLH2
tPHL2
VT
VOH
VT
VOL
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
VOH
VOL
tPLH
tPHL
tPLH
OUTPUT
VIH
VT
VIH
VT
LVC Link
DATA
INPUT
0V
tREM
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
tSU
tH
tSU
tH
VIH
VT
VIH
VT
VIH
VT
VIH
VT
LVC Link
LOW -HIGH-LOW
PULSE
HIGH-LOW -HIGH
PULSE
VT
tW
VT
LVC Link
CONTROL
INPUT
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SW ITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SW ITCH
OPEN
tPHZ
0V
VOL+VLZ
VOH
VT
tPZL
VLOAD/2
VIH
VT
VOL
VOH-VHZ
LVC Link
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
SWITCH POSITION
OUTPUT SKEW - tsk (x)
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
Symbol
VCC(1)= 3.3V ±0.3V
VCC(1) = 2.7V
VCC(2)= 2.5V ±0.2V
Unit
VLOAD
66
2 x Vcc
V
VIH
2.7
Vcc
V
VT
1.5
VCC / 2
V
VLZ
300
150
mV
VHZ
300
150
mV
CL
50
30
pF
LVC Link
Test
Switch
Open Drain
Disable Low
Enable Low
VLOAD
Disable High
Enable High
GND
All Other tests
Open
LVC Link
PULSE WIDTH
相关PDF资料 |
PDF描述 |
|---|---|
| IDT74LVC169AQ | LVC/LCX/Z SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL BINARY COUNTER, PDSO16 |
| IDT74LVC1G00ADY | LVC/LCX/Z SERIES, 2-INPUT NAND GATE, PDSO5 |
| IDT74LVC1G08ADY | LVC/LCX/Z SERIES, 2-INPUT AND GATE, PDSO5 |
| IDT74LVC1G08ADY8 | LVC/LCX/Z SERIES, 2-INPUT AND GATE, PDSO5 |
| IDT74LVC1G86ADY | LVC/LCX/Z SERIES, 2-INPUT XOR GATE, PDSO5 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT74LVC169AXTPG | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC2244APY | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC2245APG | 制造商:IDT (INTEGR DEVICES TECH) 功能描述: |
| IDT74LVC241AESO | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC244APGG | 功能描述:IC BUFF/DVR TRI-ST DUAL 20TSSOP RoHS:是 类别:集成电路 (IC) >> 逻辑 - 缓冲器，驱动器，接收器，收发器 系列:74LVC 标准包装:1,000 系列:74ABT 逻辑类型:寄存收发器，非反相 元件数:1 每个元件的位元数:8 输出电流高，低:32mA，64mA 电源电压:4.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。