参数资料
型号: IDT74LVCH16260APF8
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 总线收发器
英文描述: LVC/LCX/Z SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56
封装: 0.40 MM PITCH, TVSOP-56
文件页数: 1/7页
文件大小: 69K
代理商: IDT74LVCH16260APF8
INDUSTRIALTEMPERATURERANGE
IDT74LVCH16260A
3.3V CMOS 12-BIT TRI-PORT BUS EXCHANGER WITH 5V TOLERANT I/O
1
OCTOBER 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4229/2
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVCH16260A
DESCRIPTION:
The LVCH16260A tri-port bus exchanger is built using advanced dual
metal CMOS technology. The LVCH16260A is a high-speed 12-bit latched
bus multiplexer/transceiver for use in high-speed microprocessor applica-
tions. This bus exchanger supports memory interleaving with latched out-
puts on the B ports and address multiplexing with latched inputs on the B
ports.
The LVCH16260A tri-port bus exchanger has three 12-bit ports. Data
may be transferred between the A port and either/both of the B ports. The
latch enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (OE1B
and OE2B) allow reading from one port while writing to the other port.
All pins of the 12-bit Bus Exchanger can be driven from either 3.3V or
5V devices. This feature allows the use of the device as a translator in a
mixed 3.3V/5V supply system.
The LVCH16260A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16260A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 12-BIT
TRI-PORT BUS EXCHANGER
WITH 5 VOLT TOLERANT I/O
AND BUS-HOLD
LE1B
LEA1B
OE1B
SE L
OEA
A1:12
LE2B
LEA2B
OE2B
A-1B
LATC H
1B -A
LATC H
A-2B
LATC H
2B -A
LATC H
M
U
X
1
0
12
1B1:12
2B1:12
12
29
30
2
28
1
27
56
55
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