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参数资料
| 型号： | IDT74LVCH574APG8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 总线收发器 |
| 英文描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封装： | TSSOP-20 |
| 文件页数： | 2/6页 |
| 文件大小： | 63K |
| 代理商： | IDT74LVCH574APG8 |
INDUSTRIALTEMPERATURERANGE
2
IDT74LVCH574A
3.3VCMOSOCTALEDGE-TRIGGEREDD-TYPEFLIP-FLOP
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
5.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
–50
mA
IOK
VI < 0 or VO < 0
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
3
1
D
VCC
16
15
14
5
Q
4
Q
6
Q
2
Q
1
Q
3
Q
11
8
Q
7
Q
CLK
19
18
20
17
13
12
OE
5
6
D
7
4
D
5
D
4
2
D
3
D
8
9
GND
10
7
D
8
D
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
↑ = LOW-to-HIGH Transition
2. Output level before the indicated steady-state input conditions were established.
Inputs
Outputs
OE
CLK
xD
xQ
L
↑
HH
L
↑
LL
L
H or L
X
Q(2)
HX
X
Z
FUNCTION TABLE (EACHFLIP-FLOP)(1)
Pin Names
Description
OE
Output Enable Inputs (Active LOW)
CLK
Clock Input
xD
Data Inputs(1)
xQ
3-State Outputs
PIN DESCRIPTION
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