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参数资料
| 型号： | IDT77V500S25PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 10/17页 |
| 文件大小： | 0K |
| 描述： | IC SW MEMORY 8X8 1.2BGPS 100TQFP |
| 标准包装： | 750 |
| 系列： | SwitchStar™ |
| 类型： | 集成式开关控制器 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 带卷 (TR) |
| 其它名称： | 77V500S25PF8 |
2 of 17
April 11, 2001
IDT77V500
The IDT77V500 utilizes Per Virtual Connection (VC) Queuing to keep
track of each call, and has the capacity to keep track of as many as 8192
individual VC queues. There are four possible priorities available for
each of the assigned outputs of the Switching Memory, and CBR, VBR,
UBR, and ABR-EFCI service classes are supported by the Switch
Controller. Multicasting and broadcasting services are provided,
requiring only the appropriate header information to execute these oper-
ations automatically without requiring multiple Switching Memory
entries.
The IDT77V500 also has a mode for managing and transmitting
packetized data, enabling easy transition between packet oriented
networks such as Ethernet and FDDI and ATM cell oriented networks.
The IDT77V500 has an 8-bit Manager Bus interface, MDATA0-7, to a
Call Setup Manager processor for the configuration activity and call
setup operation. When a Call Setup Cell is received by the IDT77V400,
the cell is directed to a specified output port and the payload processed
by the Call Setup Manager. The new Virtual Connection (VC) is then
established in the Queue Manager of the IDT77V500, with all operations
executed across the 8-bit Manager Bus. Subsequent cells of that partic-
ular VC are then prioritized and directed by the Switch Controller as they
are received by the IDT77V400; no further interaction with the Call
Manager processor is required for ongoing queue and cell management.
The IDT77V500 supports a major subset of the available commands
and configurations of the IDT77V400 Switching Memory. Please refer to
the SwitchStar User Manual for additional feature details and implemen-
tation information.
The IDT77V500 is fully 3.3V LVTTL compatible, and is packaged in
an 100-pin Thin Plastic Quad Flatpack (TQFP) and an 144-ball BGA.
Functional Block Diagram
1SCLK and Reset are inputs to all blocks.
2Outputs are always enabled (active).
IOD0-31
32
Control
Logic
OFRM0-7
CRCERR
SCLK
CMD0-5
6
3607 drw 02
Call
Setup
Manager
MDATA0-7
MSTRB
MD/C
MR/W
Switching Memory Interface
Output
Service
and
Arbitration
State
Machine
Queue Manager
Output Queues
and
Link Registers
RESETI
RESETO
CBRCLK2
CBRCLK3
SFRM
Reset1
SCLK1
2
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