参数资料
型号: IDT77V500S25PF8
厂商: IDT, Integrated Device Technology Inc
文件页数: 17/17页
文件大小: 0K
描述: IC SW MEMORY 8X8 1.2BGPS 100TQFP
标准包装: 750
系列: SwitchStar™
类型: 集成式开关控制器
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-TQFP(14x14)
包装: 带卷 (TR)
其它名称: 77V500S25PF8
9 of 17
April 11, 2001
IDT77V500
Control Interface Timing Waveform
This waveform describes the command interaction across the IOD Bus to the IDT77V400 Switching Memory.
1The result of this GET STATUS command is that an ISAM is full and ready to be stored to the Cell Memory of the IDT77V400.
Control Interface Commands
Control Interface Commands(1)
(1)
SFRM, CBUS, and OFRM Timing Waveforms
1OFRM1-7 become CBUS1-7 (Outputs) during cell bus operations to arbitrate between multiple IDT77V500's.
Command1
1. CMD bus commands not defined in this table are undefined and are not implemented by the IDT77V500.
Command Description
Command Bus Bit (CMD5:0)
MSb
LSb
54
3210
GHIx
Get Header from ISAMx2
2. "x" represents the specific ISAM or OSAM being accessed (IP0-IP7 or OP0-OP7 respectively).
00
1n3
3. "n" represents the appropriate bit of the binary representation of the ISAM or OSAM being accessed (000 to 111).
GST
Get ISAM Status Register Bits
01
0010
GER
Get Error Register Bits
01
0110
STEx
Store Cell in ISAMx2 and Edit Buffer in Memory
1
0
LDOx
Load Cell from Memory into OSAMx2
11
PHE
Put new Header in Edit Buffer
1
1100
PHEC
Put new Header and new CRC byte in Edit Buffer
1
1101
REF
Refresh Cell Memory
01
0111
LDC
Load Configuration Register
1
1010
OHE
Put new Header in Output Edit Register
1
1110
OHEC
Put new Header and new CRC byte in Output Edit Register
1
1001
GET
STATUS
STORE
ISAM
PUT
HEADER
GET
HEADER ISAM
GET
STATUS
SCLK
CRCERR
3607 drw 06
CMD0-5
IOD0-31
Input -
Old Header
[CRC ERROR = LOW ]
Output -
New Header
[ AVAILABLE FOR NEXT COMMAND ]
Output -
Cell Addr
tCYC
tCH
tCL
tCDC
tDCC
tSIO
tSCRC tHCRC
tCDIO
tDCIO
STATUS
1
tHIO
1
tCDIO
tDCIO
SCLK
OFRM
3607 drw 07
tOFP
OFRM/CBUS
tCDOF
tDCOF
1
SFRM
tDCS
tCDS
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