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参数资料
| 型号： | IDT79RV3081-25DL8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 25 MHz, RISC PROCESSOR, PQCC84 |
| 封装： | 0.050 INCH PITCH, HEAT SINK, PLASTIC, LCC-84 |
| 文件页数： | 34/41页 |
| 文件大小： | 893K |
| 代理商： | IDT79RV3081-25DL8 |
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5.5
4
IDT79R3081 RISController
MILITARY AND COMMERCIAL TEMPERATURE RANGES
a double frequency clock. The 2x clock mode is provided for
compatiblity with the R3051. The clock generator unit replaces
the external delay line required in R3000A based applications.
Instruction Cache
The R3081 implements a 16kB Instruction Cache. The
system may choose to repartition the on-chip caches, so that
the instruction cache is reduced to 8kB but the data cache is
increased to 8kB. The instruction cache is organized with a
line size of 16bytes (four entries). This large cache achieves
hit rates in excess of 98% in most applications, and substantially
contributes to the performance inherent in the R3081. The
cache is implemented as a direct mapped cache, and is
capable of caching instructions from anywhere within the 4GB
physical address space. The cache is implemented using
physical addresses (rather than virtual addresses), and thus
does not require flushing on context switch.
The instruction cache is parity protected over the instruction
word and tag fields. Parity is generated by the read buffer
during cache refill; during cache references, the parity is
checked, and in the case of a parity error, a cache miss is
processed.
Data Cache
The R3081 incorporates an on-chip data cache of 4kB,
organized as a line size of 4 bytes (one word). The R3081
allows the system to reconfigure the on-chip cache from the
default 16kB I-Cache/4kB D-Cache to 8kB of Instruction and
8kB of Data caches.
The relatively large data cache achieves hit rates in excess
of 95% in most applications, and contributes substantially to
the performance inherent in the R3081. As with the instruction
cache, the data cache is implemented as a direct mapped
physical address cache. The cache is capable of mapping any
word within the 4GB physical address space.
The data cache is implemented as a write-through cache,
to insure that main memory is always consistent with the
internal cache. In order to minimize processor stalls due to
data write operations, the bus interface unit incorporates a 4-
deep write buffer which captures address and data at the
processor execution rate, allowing it to be retired to main
memory at a much slower rate without impacting system
performance. Further, support has been provided to allow
hardware based data cache coherency in a multi-master
environment, such as one utilizing DMA from I/O to memory.
The data cache is parity protected over the data and tag
fields. Parity is generated by the read buffer during cache refill;
during cache references, the parity is checked, and in the case
of a parity error, a cache miss is processed.
Bus Interface Unit
The R3081 uses its large internal caches to provide the
majority of the bandwidth requirements of the execution
engine, and thus can utilize a simple bus interface connected
to slower memory devices. Alternately, a high-performance,
low-cost secondary cache can be implemented, allowing the
processor to increase performance in systems where bus
bandwidth is a performance limitation.
As part of the R3051 family, the R3081 bus interface utilizes
a 32-bit address and data bus multiplexed onto a single set of
pins. The bus interface unit also provides an ALE (Address
Latch Enable) output signal to de-multiplex the A/D bus, and
Figure 5. FPA Functional Block Diagram
Cache
Data
Data Bus
Instructions
Operands
Condition
Codes
Exponent Part
Fraction
Register Unit (16 X 64)
(32)
Control Unit
and Clocks
(11)
(53)
(56)
(53)
(56)
A
B
Result
Exponent
Unit
AB
Add Unit
Round
Result
AB
Result
AB
Divide Unit
Multiply Unit
2889 drw 05
相关PDF资料 |
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| IDT79RV3081-40DL8 | 32-BIT, 40 MHz, RISC PROCESSOR, PQCC84 |
| IDT79RV3081-25DL | 32-BIT, 25 MHz, RISC PROCESSOR, PQCC84 |
| IDT79R3081E-40DL8 | 32-BIT, 40 MHz, RISC PROCESSOR, PQCC84 |
| IDT79R3081E-25DL8 | 32-BIT, 25 MHz, RISC PROCESSOR, PQCC84 |
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