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参数资料
| 型号： | IDT79RV3081-25DL8 |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 25 MHz, RISC PROCESSOR, PQCC84 |
| 封装： | 0.050 INCH PITCH, HEAT SINK, PLASTIC, LCC-84 |
| 文件页数： | 39/41页 |
| 文件大小： | 893K |
| 代理商： | IDT79RV3081-25DL8 |
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IDT79R3081 RISController
MILITARY AND COMMERICAL TEMPERATURE RANGES
5.5
7
many general purpose computing applications, such as ARC
compliant systems.
Autonomous multiply and divide operations. The R3051
family features an on-chip integer multiplier/divide unit which is
separate from the other ALU. This allows the CPU to perform
multiply or divide operations in parallel with other integer oper-
ations, using a single multiply or divide instruction rather than
“step” operations.
Integrated write buffer. The R3081 features a four deep
write buffer, which captures store target addresses and data at
the processor execution rate and retires it to main memory at
the slower main memory access rate. Use of on-chip write
buffers eliminates the need for the processor to stall when per-
forming store operations.
Burst read support. The R3051 family enables the system
designer to utilize page mode or nibble mode RAMs when per-
forming read operations to minimize the main memory read
penalty and increase the effective cache hit rates.
These techniques combine to allow the processor to
achieve over 43 VUPS integer performance, 13MFlops of Lin-
pack performance, and 70,000 dhrystones without the use of
external caches or zero wait-state memory devices.
The performance differences between the various family
members depends on the application software and the design
of the memory system. The impact of the various cache sizes,
and the hardware floating point, can be accurately modeled
using Cache-3051. Since the R3041, R3051, R3052, R3071,
and R3081 are all pin and software compatible, the system
designer has maximum freedom in trading between perfor-
mance and cost. A system can be designed, and later the
appropriate CPU inserted into the board, depending on the
desired system performance.
SELECTABLE FEATURES
The R3081 allows the system designer to configure certain
aspects of operation. Some of these options are established
when the device is reset, while others are enabled via the
Config registers:
BigEndian vs. LittleEndian Byte Ordering. The part can be
configured to operate with either byte ordering. ACE/ARC sys-
tems typically use Little Endian byte ordering. However, vari-
ous embedded applications, written originally for a Big Endian
processor such as the MC680x0, are easier to port to a Big
Endian system.
Data Cache Refill of one or four words. The memory sys-
tem must be capable of performing four word refills of instruc-
tion cache misses. The R3081 allows the system designer to
enable D-Cache refill of one or four words dynamically. Thus,
specialized algorithms can choose one refill size, while the
rest of the system can operate with the other.
Half-frequency bus mode. The processor can be config-
ured such that the external bus interface is at one-half the fre-
quency of the processor core. This simplifies system design;
however, the large on-chip caches mitigate the performance
impact of using a slower system bus clock.
Slow bus turn-around. The R3081 allows the system
designer to space processor operations, so that more time
is allowed for transitions between memory and the processor
on the multiplexed address/data bus.
Configurable cache. The R3081 allows the system designer
to use software to select either a 16kB Instruction Cache/4kB
Data Cache organization, or an 8kB Instruction/8kB Data
Cache organization.
Cache Coherent Interface. The R3081 has an optional
hardware based cache coherency interface intended to sup-
port multi-master systems such as those utilizing DMA
between memory and I/O.
Optional 1x or 2x clock input. The R3081 can be driven
with an R3051 compatible 2x clock input, or a lower frequency
1x clock input.
THERMAL CONSIDERATIONS
The R3081 utilizes special packaging techniques to
improve the thermal properties of high-speed processors.
Thus, the R3081 is packaged using cavity down packaging,
with an embedded thermal slug to improve thermal transfer to
the surrounding air.
The R3081 utilizes the 84-pin plastic package, with the die
being attached to a heat slug. The DL84 package allows for an
efficient thermal transfer between the die and the heat slug.
The heat slug offers a greater area for convection at any given
temperature. Even nominal amounts of airflow will dramatically
reduce the junction temperature of the die, resulting in cooler
operation. The DL84 package is available at all frequencies,
and is pin and form compatible with the PLCC used for the
R3051. Thus, designers can interchange R3081s and R3051s
in a particular design, without changing their PC Board.
The R3081 is guaranteed in a case temperature range of
0°C to +85°C. The type of package, speed (power) of the
device, and airflow conditions, affect the equivalent ambient
temperature conditions which will meet this specification.
The equivalent allowable ambient temperature, TA, can be
calculated using the thermal resistance from case to ambient
(CA) of the given package. The following equation relates
ambient and case temperature:
TA = TC - P * CA
where P is the maximum power consumption at hot tem-
perature, calculated by using the maximum Icc specification
for the device.
Typical values for CA at various airflows are shown in
Table 1.
Note that the R3081 allows the operational frequency to be
turned down during idle periods to reduce power consumption.
This operation is described in the R3081 Hardware User's
Guide. Reducing the operation frequency dramatically
reduces power consumption.
相关PDF资料 |
PDF描述 |
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| IDT79RV3081-40DL8 | 32-BIT, 40 MHz, RISC PROCESSOR, PQCC84 |
| IDT79RV3081-25DL | 32-BIT, 25 MHz, RISC PROCESSOR, PQCC84 |
| IDT79R3081E-40DL8 | 32-BIT, 40 MHz, RISC PROCESSOR, PQCC84 |
| IDT79R3081E-25DL8 | 32-BIT, 25 MHz, RISC PROCESSOR, PQCC84 |
| IDT79RV4400PC-75G | 64-BIT, 75 MHz, RISC PROCESSOR, CPGA179 |
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