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参数资料
| 型号： | IDT82V2084PF8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 2/75页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 4CH 128-TQFP |
| 标准包装： | 1,000 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 带卷 (TR) |
| 其它名称： | 82V2084PF8 |
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10
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
RD1/RDP1
RD2/RDP2
RD3/RDP3
RD4/RDP4
CV1/RDN1
CV2/RDN2
CV3/RDN3
CV4/RDN4
Output
93
87
77
71
92
86
76
70
RDn: Receive Data for Channel 1~4
In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI, HDB3 or B8ZS line code
rules. The active level on RDn pin is selected by the RD_INV bit (RCF0, 07H...).
CVn: Code Violation for Channel 1~4
In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn to high level for a full clock
cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/HDB3 decoder is enabled. When AMI decoder is
selected, the bipolar violation can be indicated.
RDPn/RDNn: Positive/Negative Receive Data for Channel 1~4
In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recovered clock. An active level
on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while an active level on RDNn indicates the receipt of a neg-
ative pulse on RTIPn/RRINGn. The active level on RDPn/RDNn is selected by the RD_INV bit (RCF0, 07H...). When CDR is
disabled, these pins directly output the raw RZ sliced data. The output data on RDn and RDPn/RDNn is updated on the active
edge of RCLKn.
RCLK1
RCLK2
RCLK3
RCLK4
Output
94
88
78
72
RCLKn: Receive Clock for Channel 1~4
These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions, if AISE bit
(MAINT0, 0AH...) is ‘1’, RCLKn is derived from MCLK.
In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/RRINGn. The receive data
(RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on the active edge of RCLKn. The active edge is
selected by the RCLK_SEL bit (RCF0, 07H...).
If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data RDPn and RDNn. This signal
can be used in the applications with external clock recovery circuitry.
MCLK
Input
10
MCLK: Master Clock
MCLK is an independent, free-running reference clock. It is a single reference for all operation modes and provides selectable
1.544 MHz or 37.056 MHz for T1/J1 operating mode, while 2.048 MHz or 49.152 MHz for E1 operating mode.
The reference clock is used to generate several internal reference signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLKn signal during a loss of signal condition.
Reference clock during Transmit All Ones (TAO) and all zeros condition. When sending PRBS/QRSS or Inband Loopback
code, either MCLK or TCLKn can be selected as the reference clock.
Reference clock for ATAO and AIS.
The loss of MCLK will turn all the four TTIP/TRING into high impedance status.
MCLKS
Input
40
MCLKS: Master Clock Select
If 2.048 MHz (E1) or 1.544 MHz (T1/J1) is selected as the MCLK, this pin should be connected to ground; and if the 49.152 MHz
(E1) or 37.056 MHz (T1/J1) is selected as the MCLK, this pin should be pulled high.
LOS1
LOS2
LOS3
LOS4
Output
128
1
2
3
LOSn: Loss of Signal Output for Channel 1~4
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received sig-
nals in channel n. The LOSn pin will become low automatically when valid received signal is detected again. The criteria of loss
of signal are described in 3.5 LOS AND AIS DETECTION.
Control Interface
P/S
Input
8
P/S: Parallel or Serial Control Interface Select
Level on this pin determines which control mode is selected to control the device as follows:
The serial microcontroller interface consists of CS, SCLK, SDI, SDO and SCLKE pins. Parallel microcontroller interface consists
of CS, A[7:0], D[7:0], DS/RD and R/W/WR pins. The device supports non-multiplexed parallel interface as follows:
Table-1 Pin Description (Continued)
Name
Type
TQFP128
Description
P/S
Control Interface
High
Parallel Microcontroller Interface
Low
Serial Microcontroller Interface
P/S, INT/MOT
Microcontroller Interface
10
Motorola non-multiplexed
11
Intel non-multiplexed
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相关代理商/技术参数 |
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| IDT82V2084PFG | 功能描述:IC LIU T1/J1/E1 4CH 128-TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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| IDT82V2088 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
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| IDT82V2088BB | 功能描述:IC LIU T1/J1/E1 8CH 208-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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