参数资料
型号: IDT82V2084PF
厂商: IDT, Integrated Device Technology Inc
文件页数: 48/75页
文件大小: 0K
描述: IC LIU T1/J1/E1 4CH 128-TQFP
标准包装: 15
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 128-LQFP
供应商设备封装: 128-TQFP(14x20)
包装: 托盘
其它名称: 82V2084PF
52
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.9
COUNTER REGISTERS
Table-52 INTS1: Interrupt Status Register 1
(this register is reset and relevant interrupt request is cleared after a read) (R, Address = 17H, 57H,97H, D7H)
Symbol
Bit
Default
Description
DAC_OV_IS
7
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.
= 0: no pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
JAOV_IS
6
0
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: no JA overflow interrupt event occurred
= 1: A overflow interrupt event occurred
JAUD_IS
5
0
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: no JA underflow interrupt event occurred
= 1: JA underflow interrupt event occurred
ERR_IS
4
0
This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: no PRBS/QRSS logic error interrupt event occurred
= 1: PRBS/QRSS logic error interrupt event occurred
EXZ_IS
3
0
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: no excessive zeros interrupt event occurred
= 1: EXZ interrupt event occurred
CV_IS
2
0
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: no code violation interrupt event occurred
= 1: code violation interrupt event occurred
TMOV_IS
1
0
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: no one-second timer expiration interrupt event occurred
= 1: one-second timer expiration interrupt event occurred
CNT_OV_IS
0
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: no counter overflow interrupt event occurred
= 1: counter overflow interrupt event occurred
Table-53 CNT0: Error Counter L-byte Register 0
(R, Address = 18H, 58H,98H, D8H)
Symbol
Bit
Default
Description
CNT_L[7:0]
7-0
00H
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
Table-54 CNT1: Error Counter H-byte Register 1
(R, Address = 19H, 59H,99H,D9H)
Symbol
Bit
Default
Description
CNT_H[7:0]
7-0
00H
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
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