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| 型号： | IDT82V2084PFG |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 27/75页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/J1/E1 4CH 128-TQFP |
| 标准包装： | 15 |
| 类型： | 线路接口装置（LIU） |
| 规程： | E1 |
| 电源电压： | 3.13 V ~ 3.47 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 128-LQFP |
| 供应商设备封装： | 128-TQFP（14x20） |
| 包装： | 托盘 |
| 其它名称： | 82V2084PFG |
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33
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
3.12 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2084 are indicated by the INT pin.
When the INT_PIN[0] bit (GCF0, 40H) is ‘0’, the INT pin is open drain active
low, with a 10 K
external pull-up resistor. When the INT_PIN[1:0] bits
(GCF0, 40H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
All the interrupt can be disabled by the INTM_GLB bit (GCF0, 40H).
When the INTM_GLB bit (GCF0, 40H) is set to ‘0’, an active level on the
INT pin represents an interrupt of the IDT82V2084. The INT_CH[7:0] bits
(INTCH, 80H) should be read to identify which channel(s) generate the
interrupt.
The interrupt event is captured by the corresponding bit in the Interrupt
Status Register (INTS0, 16H...) or (INTS1, 17H...). Every kind of interrupt
canbeenabled/disabledindividuallybythecorresponding bitinthe register
(INTM0, 11H...) or (INTM1, 12H...). Some event is reflected by the corre-
sponding bit in the Status Register (STAT0, 14H...) or (STAT1, 15H...), and
theInterruptTriggerEdgeSelectionRegistercanbeusedtodeterminehow
the Status Register sets the Interrupt Status Register.
After the Interrupt Status Register (INTS0, 16H...) or (INTS1, 17H...) is
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (80H) will be reset. Only when all the pending
interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 16H...) or (INTS1, 17H...) will all the bits in the
INTCH register (80H) be reset and the INT pin become inactive.
There are totally fourteen kinds of events that could be the interrupt
source for one channel:
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).Inband Loopback Code Status
(11).Equalizer Out of Range
(12).One-Second Timer Expired
(13).Error Counter Overflow
(14).Arbitrary Waveform Generator Overflow
Table-22 is a summary of all kinds of interrupt and their associated Sta-
tus bit, Interrupt Status bit, Interrupt TriggerEdge Selectionbit andInterrupt
Mask bit.
3.13 5V TOLERANT I/O PINS
All digital input pins will tolerate 5.0 ± 5% volts and are compatible with
TTL logic.
3.14 RESET OPERATION
The chip can be reset in two ways:
Software Reset: Writing to the RST register (20H) will reset the chip
in 1 us.
Hardware Reset: Asserting the RST pin low for a minimum of 100 ns
will reset the chip.
After reset, all drivers output are in high impedance state, all the internal
flip-flops are reset, and all the registers are initialized to default values.
3.15 POWER SUPPLY
This chip uses a single 3.3 V power supply.
Table-22 Interrupt Event
Interrupt Event
Status bit
(STAT0, STAT1)
Interrupt Status bit
(INTS0, INTS1)
Interrupt Edge Selection bit
(INTES)
Interrupt Mask bit
(INTM0, INTM1)
LOS Detected
LOS_S
LOS_IS
LOS_IES
LOS_IM
AIS Detected
AIS_S
AIS_IS
AIS_IES
AIS_IM
Driver Failure Detected
DF_S
DF_IS
DF_IES
DF_IM
TCLKn Loss
TCLK_LOS
TCLK_LOS_IS
TCLK_IES
TCLK_IM
Synchronization Status of PRBS/QRSS
PRBS_S
PRBS_IS
PRBS_IES
PRBS_IM
PRBS/QRSS Error
ERR_IS
ERR_IM
Code Violation Received
CV_IS
CV_IM
Excessive Zeros Received
EXZ_IS
EXZ_IM
JA FIFO Overflow
JAOV_IS
JAOV_IM
JA FIFO Underflow
JAUD_IS
JAUD_IM
Equalizer Out of Range
EQ_S
EQ_IS
EQ_IES
EQ_IM
Inband Loopback Activate Code Status
IBLBA_S
IBLBA_IS
IBLBA_IES
IBLBA_IM
Inband Loopback Deactivate Code Status
IBLBD_S
IBLBD_IS
IBLBD_IES
IBLBD_IM
One-Second Timer Expired
TMOV_IS
TIMER_IM
Error Counter Overflow
CNT_OV_IS
CNT_IM
Arbitrary Waveform Generator Overflow
DAC_OV_IS
DAC_OV_IM
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V2084PFG8 | 功能描述:IC LINE INTERFC UNIT 4CH 128TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2088 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2088_08 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:OCTAL CHANNEL T1/E1/J1 LONG HAUL/ SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2088BB | 功能描述:IC LIU T1/J1/E1 8CH 208-BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| IDT82V2088BBG | 功能描述:IC LINE INTERFACE UNIT 208-PBGA RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:250 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
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