参数资料
型号: IDT82V2088DRG
厂商: IDT, Integrated Device Technology Inc
文件页数: 36/78页
文件大小: 0K
描述: IC LIU T1/J1/E1 8CH 208-TQFP
标准包装: 12
类型: 线路接口装置(LIU)
规程: E1
电源电压: 3.13 V ~ 3.47 V
安装类型: 表面贴装
封装/外壳: 208-BFQFP
供应商设备封装: 208-PQFP(28x28)
包装: 托盘
其它名称: 82V2088DRG
41
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
4.2.2
JITTER ATTENUATION CONTROL REGISTER
4.2.3
TRANSMIT PATH CONTROL REGISTERS
Table-31 JACF: Jitter Attenuator Configuration Register
(R/W, Address = 01H,21H,41H,61H,81H,A1H,C1H,E1H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved
JA_LIMIT
5
0
Wide Jitter Attenuation bandwidth
= 0: normal mode
= 1: JA limit mode
JACF[1:0]
4-3
00
Jitter Attenuator configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
JADP[1:0]
2-1
00
Jitter Attenuator depth selection
= 00: 128 bits
= 01: 64 bits
= 10/11: 32 bits
JABW
0
Jitter transfer function bandwidth selection
JABW
T1/J1
E1
05 Hz
6.8 Hz
1
1.25 Hz
0.9 Hz
Table-32 TCF0: Transmitter Configuration Register 0
(R/W, Address = 02H,22H,42H,62H,82H,A2H,C2H,E2H)
Symbol
Bit
Default
Description
-
7-5
000
Reserved
T_OFF
4
0
Transmitter power down enable
= 0: Transmitter power up
= 1: Transmitter power down and line driver high impedance
TD_INV
3
0
Transmit data invert
= 0: data on TDn or TDPn/TDNn is active high
= 1: data on TDn or TDPn/TDNn is active low
TCLK_SEL
2
0
Transmit clock edge select
= 0: data on TDn or TDPn/TDNn is sampled on the falling edges of TCLKn
= 1: data on TDn or TDPn/TDNn is sampled on the rising edges of TCLKn
T_MD[1:0]
1-0
00
Transmitter operation mode control bits which select different stages of transmit data path
= 00: enable HDB3/B8ZS encoder and waveform shaper blocks, input on TDn is single rail NRZ data
= 01: enable AMI encoder and waveform shaper blocks, input on pin TDn is single rail NRZ data
= 1x: encoder is bypassed, dual rail NRZ transmit data input on pin TDPn/TDNn
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