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参数资料
| 型号： | IDT82V3002A |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | WAN PLL WITH DUAL REFERENCE INPUTS |
| 中文描述： | 广域网锁相环双基准输入 |
| 文件页数： | 8/28页 |
| 文件大小： | 390K |
| 代理商： | IDT82V3002A |
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8
IDT82V3002A WAN PLL WITH DUAL REFERENCE INPUTS INDUSTRIAL TEMPERATURE RANGE
NORMAL
(CMOS) O
46
Normal Indicator.
This output goes to a logic high whenever the DPLL goes into Normal Mode.
FREERUN
(CMOS) O
51
Freerun Indicator.
This output goes to a logic high whenever the DPLL goes into Freerun Mode.
MON_out
O
7
Monitor Reference Out Of Capture Range.
A logic high at this pin indicates that the reference is off the nominal frequency by more than ±12 ppm.
C32o
(CMOS) O
25
Clock 32.768 MHz.
This output is a 32.768 MHz clock used for ST-BUS operation.
C16o
(CMOS) O
24
Clock 16.384 MHz.
This output is a 16.384 MHz clock used for ST-BUS operation.
C8o
(CMOS) O
23
Clock 8.192 MHz.
This output is an 8.192 MHz clock used for ST-BUS operation.
C4o
(CMOS) O
20
Clock 4.096 MHz.
This output is a 4.096 MHz clock used for ST-BUS operation.
C2o
(CMOS) O
17
Clock 2.048 MHz.
This output is a 2.048 MHz clock used for ST-BUS operation.
C3o
(CMOS) O
16
Clock 3.088 MHz.
This output is a 3.088 MHz clock used for T1 applications.
C1.5o
(CMOS) O
15
Clock 1.544 MHz.
This output is a 1.544 MHz clock used for T1 applications.
C6o
(CMOS) O
14
Clock 6.312 MHz.
This output is a 6.312 MHz clock used for DS2 applications.
F32o
(CMOS) O
40
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 31 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
F16o
(CMOS) O
39
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 8.192 Mb/s.
F8o
(CMOS) O
36
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
F0o
(CMOS) O
33
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
RSP
(CMOS) O
41
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
TSP
(CMOS) O
42
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is typically used
to connect to Siemens MUNICH-32 device.
TDO
(CMOS) O
29
Test Serial Data Out.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state if JTAG scan is
not enabled.
TDI
I
32
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V
DD
.
TRST
I
30
Test Reset.
Asynchronously initializes the JTAG TAP controller by putting it in Test-Logic-Reset state. This pin is internally pulled up
to V
DD
. It is connected to the ground for normal applications.
Table - 1 Pin Description (Continued)
Name
Type
Pin
Number
Description
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PDF描述 |
|---|---|
| IDT82V3002APV | WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3010 | T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS |
| IDT82V3010PV | T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS |
| IDT82V3010PVG | T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS |
| IDT82V3255 | WAN PLL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3002A_08 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002A-01PVG | 功能描述:IC PLL WAN T1/E1 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3002A-01PVG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN T1/E1 56SSOP |
| IDT82V3002APV | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:WAN PLL WITH DUAL REFERENCE INPUTS |
| IDT82V3002APVG | 功能描述:IC PLL WAN T1/E1 DUAL REF 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
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