- 您现在的位置：买卖IC网 > PDF目录377488 > IDT82V3010PVG (INTEGRATED DEVICE TECHNOLOGY INC) T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS PDF资料下载
参数资料
| 型号： | IDT82V3010PVG |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 通信及网络 |
| 英文描述： | T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO56 |
| 封装： | GREEN, SSOP-56 |
| 文件页数： | 17/31页 |
| 文件大小： | 355K |
| 代理商： | IDT82V3010PVG |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页当前第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页
IDT82V3010
T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Measures of Performance
17
June 19, 2006
period. Usually, the given timing signal and the ideal timing signal are of
the same frequency. Phase continuity applies to the output of the
synchronizer after a signal disturbance due to a mode change. The
observation period is usually the time from the disturbance, to just after
the synchronizer has settled to a steady state.
In the case of the IDT82V3010, the output signal phase continuity is
maintained to within ±5 ns at the instance (over one frame) of all mode
changes. The total phase shift, depending on the type of mode change,
may accumulate up to 200 ns over many frames. The rate of change of
the 200 ns phase shift is limited to a maximum phase slope of
approximately 5 ns per 125 μs. This meets the AT&T TR62411
maximum phase slope requirement of 7.6 ns per 125 μs.
3.12
PHASE LOCK TIME
This is the time it takes the synchronizer to phase lock to the input
signal. Phase lock occurs when the input signal and output signal are
not changing in phase with respect to each other (not including jitter).
Lock time is very difficult to determine because it is affected by many
factors including:
1. Initial input to output phase difference
2. Initial input to output frequency difference
3. Synchronizer loop filter
4. Synchronizer limiter
Although a short lock time is desirable, it is not always possible to
achieve due to other synchronizer requirements. For instance, better
jitter transfer performance is achieved with a lower frequency loop filter
which increases lock time. And better (smaller) phase slope
performance (limiter) results in longer lock times. The IDT82V3010 loop
filter and limiter are optimized to meet the AT&T TR62411 jitter transfer
and phase slope requirements. Consequently, phase lock time, which is
not a standard requirement, may be longer than in other applications.
See
“7.1 Performance”
for details.
The IDT82V3010 provides a FLOCK pin to enable the Fast Lock
mode. When this pin is set to high, the DPLL will lock to an input
reference within approximately 500 ms.
相关PDF资料 |
PDF描述 |
|---|---|
| IDT82V3255 | WAN PLL |
| IDT82V3255DK | WAN PLL |
| IDT82V3255DKG | WAN PLL |
| IDT82V3255TF | WAN PLL |
| IDT82V3255TFG | WAN PLL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDT82V3010PVG8 | 功能描述:IC PLL WAN 51/E1/OC3 DUAL 56SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3011 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:T1/E1/OC3 WAN PLL WITH SINGLE REFERENCE INPUT |
| IDT82V3011PV | 制造商:INT_DEV_TECH 功能描述: |
| IDT82V3011PVG | 功能描述:IC PLL WAN T1/E1/OC3 SGL 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
| IDT82V3011PVG8 | 功能描述:IC PLL WAN T1/E1/OC3 SGL 56-SSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:1,500 系列:- 类型:时钟缓冲器/驱动器 PLL:是 主要目的:- 输入:- 输出:- 电路数:- 比率 - 输入:输出:- 差分 - 输入:输出:- 频率 - 最大:- 电源电压:3.3V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:带卷 (TR) 其它名称:93786AFT |
发布紧急采购，3分钟左右您将得到回复。