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参数资料
| 型号： | IDTCSPT857C |
| 厂商： | Integrated Device Technology, Inc. |
| 英文描述： | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| 中文描述： | 为2.5V - 2.6V的锁相环微分1:10 SDRAM的时钟驱动器 |
| 文件页数： | 5/15页 |
| 文件大小： | 148K |
| 代理商： | IDTCSPT857C |
5
IDTCSPT857C
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (TSSOP/TV SOP)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN
, FBIN
FBOUT,
FBOUT
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
PWRDWN
V
DDQ
4, 11, 12, 15, 21, 28, 34, 38, 45
Y
[0:9]
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
Y
[0:9]
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Pin Number
17
16
13, 14
35, 36
32, 33
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
37
PIN DES CRIPT ION (V FBGA)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN
, FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
H1
G2
F1, F2
F5, F6
H6, G5
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
E6
B3, B4, E1, E2, E5, G1, G6, J3, J4
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
AV
DD
Supply Voltage
V
DDQ
I/O Supply Voltage
Min.
Typ.
V
DDQ
2.5
2.6
Max.
2.7
2.7
2.7
+85
Unit
V
V
V
DDQ
– 0.12
2.3
2.5
-40
PC1600-PC2700
PC3200
T
A
Operating Free-Air Temperature
°
C
PIN DES CRIPT ION (MLF)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN
, FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
9
8
5, 6
25, 26
21, 22
1, 10
27
Description
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
4, 7, 13, 18, 23, 24, 28, 33, 38
3, 12, 14, 17, 19, 29, 32, 34, 37, 39
2, 11, 15, 16, 20, 30, 31, 35, 36, 40
相关PDF资料 |
PDF描述 |
|---|---|
| IDTCSPT857CBV | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CBVI | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNLG | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNLGI | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNLI | 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IDTCSPT857CBV | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CBVG | 功能描述:IC PLL CLK DVR SDRAM 56-VFBGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| IDTCSPT857CBVG8 | 功能描述:IC PLL CLK DVR SDRAM 56-VFBGA RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 专用 系列:- 标准包装:28 系列:- 类型:时钟/频率发生器 PLL:是 主要目的:Intel CPU 服务器 输入:时钟 输出:LVCMOS 电路数:1 比率 - 输入:输出:3:22 差分 - 输入:输出:无/是 频率 - 最大:400MHz 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-TFSOP （0.240"，6.10mm 宽） 供应商设备封装:64-TSSOP 包装:管件 |
| IDTCSPT857CBVI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857CNL | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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