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参数资料
| 型号： | IDTCSPT857DPAGI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 11/15页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DVR SDRAM 48-TSSOP |
| 标准包装： | 2,000 |
| 类型： | 时钟缓冲器/驱动器，零延迟缓冲器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 存储器，DDR，SDRAM |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:10 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 220MHz |
| 电源电压： | 2.3 V ~ 2.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | CSPT857DPAGI8 |
5
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIALTEMPERATURERANGE
PIN DESCRIPTION (TSSOP/TVSOP)
Pin Name
Pin Number
Description
AGND
17
Ground for analog supply
AVDD
16
Analog supply
CLK,
CLK
13, 14
Differentialclockinput
FBIN, FBIN
35, 36
Feedbackdifferentialclockinput
FBOUT,
FBOUT
32, 33
Feedbackdifferentialclockoutput
GND
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
Ground
PWRDWN
37
Output enable for Y and
Y
VDDQ
4, 11, 12, 15, 21, 28, 34, 38, 45
I/O supply
Y[0:9]
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
Buffered output of input clock, CLK
Y[0:9]
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Buffered output of input clock,
CLK
PIN DESCRIPTION (VFBGA)
Pin Name
Pin Number
Description
AGND
H1
Ground for analog supply
AVDD
G2
Analog supply
CLK,
CLK
F1, F2
Differentialclockinput
FBIN, FBIN
F5, F6
Feedbackdifferentialclockinput
FBOUT,
FBOUT
H6, G5
Feedbackdifferentialclockoutput
GND
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
Ground
PWRDWN
E6
Output enable for Y and
Y
VDDQ
B3, B4, E1, E2, E5, G1, G6, J3, J4
I/O supply
Y[0:9]
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
Buffered output of input clock, CLK
Y[0:9]
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Buffered output of input clock,
CLK
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
AVDD
Supply Voltage
VDDQ– 0.12
VDDQ
2.7
V
VDDQ
I/O Supply Voltage
PC1600-PC2700
2.3
2.5
2.7
V
PC3200
2.5
2.6
2.7
TA
OperatingFree-AirTemperature
0
+70
° C
PIN DESCRIPTION (VFQFPN)
Pin Name
Pin Number
Description
AGND
9
Ground for analog supply
AVDD
8
Analog supply
CLK,
CLK
5, 6
Differentialclockinput
FBIN, FBIN
25, 26
Feedbackdifferentialclockinput
FBOUT,
FBOUT
21, 22
Feedbackdifferentialclockoutput
GND
1, 10
Ground
PWRDWN
27
Output enable for Y and
Y
VDDQ
4, 7, 13, 18, 23, 24, 28, 33, 38
I/O supply
Y[0:9]
3, 12, 14, 17, 19, 29, 32, 34, 37, 39
Buffered output of input clock, CLK
Y[0:9]
2, 11, 15, 16, 20, 30, 31, 35, 36, 40
Buffered output of input clock,
CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDTCSPT857DPAI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPFI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DVFQFPN | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DVFQFPNI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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