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参数资料
| 型号： | IDTCSPT857DPAGI8 |
| 厂商： | IDT, Integrated Device Technology Inc |
| 文件页数： | 6/15页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DVR SDRAM 48-TSSOP |
| 标准包装： | 2,000 |
| 类型： | 时钟缓冲器/驱动器，零延迟缓冲器，多路复用器 |
| PLL： | 是 |
| 主要目的： | 存储器，DDR，SDRAM |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:10 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 220MHz |
| 电源电压： | 2.3 V ~ 2.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 48-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | CSPT857DPAGI8 |
14
COMMERCIALTEMPERATURERANGE
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
APPLICATION INFORMATION
CSPT857D
C = 14pF
R = 120
Ω
FBIN
C = 14pF
R = 120
Ω
CLK
Feedback path
R = 120
Ω
Z = 60
Ω
Z = 60
Ω
8 more
SDRAM
~2.5"
~0.3"
~0.6" (split to terminator)
(1)
CSPT857D
C = 14pF
R = 120
Ω
FBIN
C = 14pF
R = 120
Ω
CLK
Feedback path
R = 120
Ω
Z = 60
Ω
Z = 60
Ω
8 more
SDRAM
~2.5"
~0.3"
~0.6" (split to terminator)
SDRAM
Stacked
(1)
Figure 9. Clock Structure 1
Figure 10. Clock Structure 2
NOTE:
1.
Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IDTCSPT857DPAI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPF | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DPFI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DVFQFPN | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
| IDTCSPT857DVFQFPNI | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER |
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