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参数资料
| 型号： | IG80C286-10 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | High Performance Microprocessor with Memory Management and Protection |
| 中文描述： | 16-BIT, 10 MHz, MICROPROCESSOR, CPGA68 |
| 文件页数： | 9/13页 |
| 文件大小： | 365K |
| 代理商： | IG80C286-10 |
3-136
80C286/883
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat
φ
1 of a processor cycle.
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
NOTES:
1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
2. The data bus will be driven as shown if the last cycle before T
I
in the diagram was a write T
C
.
3. The 80C286/883 puts its status pins in a high impedance logic one state during T
H
.
4. For HOLD request set up to HLDA, refer to Figure 8.
5. BHE and LOCK are driven at this time but will not become valid until T
S
.
6. The data bus will remain in a high impedance state if a read cycle is performed.
FIGURE 5. EXITING AND ENTERING HOLD
Waveforms
(Continued)
φ
2
BUS CYCLE TYPE
V
CH
V
CL
CLK
φ
1
PCLK
(SEE NOTE 1)
T
X
INTR, NMI
HOLD, PEREQ
(SEE NOTE 2)
ERROR, BUSY
(SEE NOTE 2)
19
19
4
5
5
4
φ
2
7
RESET
φ
1
φ
1
φ
2
6
V
CH
V
CL
CLK
(SEE NOTE 1)
T
X
V
CH
CLK
V
CL
RESET
T
X
φ
2
φ
2
φ
1
7
6
(SEE NOTE 1)
16
φ
2
φ
1
φ
2
φ
1
φ
2
φ
1
φ
2
φ
1
T
H
T
I
T
H
T
H
OR T
I
BUS CYCLE TYPE
V
CH
CLK
HILDA
V
CL
16
(SEE NOTE 4)
12A (NOTE 3)
15
(SEE NOTE 3)
12B
15
IF T
S
S1 S0
PEACK
BHE, LOCK
A
23
- A
0
,
M/IO,
COD/INTA
(SEE NOTE 5)
13
(SEE NOTE 1)
15
VALID
14
(SEE NOTE 6)
(SEE NOTE 2)
15
VALID IF WRITE
D
15
- D
0
PCLK
8
8
IF NPX TRANSFER
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| IG8200WS | 制造商:Hubbell Premise Wiring 功能描述: |
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