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| 型号： | IG80C286-12 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | High Performance Microprocessor with Memory Management and Protection |
| 中文描述： | 16-BIT, 12.5 MHz, MICROPROCESSOR, CPGA68 |
| 文件页数： | 10/13页 |
| 文件大小： | 365K |
| 代理商： | IG80C286-12 |
3-137
80C286/883
NOTES:
1. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus operation
will be either a memory read at operand address or I/O read at port address 00FA(H).
2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x
The actual, configuration dependent, maximum time is: 3 x
- 12A
MAX
-
(4)MIN
+N x 2 x
(1)
. N is the number of extra T
C
states added
to either the first or second bus operation of the processor extension data operand transfer sequence.
- 12A
MAX
-(4)
MIN
FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
NOTES:
1. Setup time for RESET
↑
may be violated with the consideration that
φ
1 of the processor clock may begin one system CLK period later.
2. Setup and hold times for RESET
↓
must be met for proper operation, but RESET
↓
may occur during
φ
1 or
φ
2.
3. The data bus is only guaranteed to be in a high impedance state at the time shown.
FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET
Waveforms
(Continued)
1
12A
φ
2
CLK
φ
1
φ
2
φ
2
φ
1
φ
2
φ
1
φ
1
φ
2
T
I
T
S
T
C
T
S
T
C
T
I
V
CH
V
CL
CLK
S1 S0
PEACK
M/IO,
A
23
-A
0
COD INTA
PEREQ
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O
PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
12B
5
4
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
BUS CYCLE TYPE
(SEE NOTE 1)
(SEE NOTE 2)
I/0 READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
1
1
12B
T
X
S1 S0
BUS CYCLE TYPE
φ
2
φ
2
φ
2
φ
2
φ
2
φ
1
φ
1
φ
1
φ
1
T
X
T
X
T
I
CLK
V
CH
V
CL
6
7
6
(SEE NOTE 1)
PEACK
A
23
- A
0
BHE
M/IO
COD/INTA
AT LEAST
16 CLK PERIODS
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
13
13
13
15
(SEE NOTE 3)
LOCK
DATA
HILDA
16
(SEE NOTE 2)
RESET
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