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参数资料
| 型号： | IG80C286-12 |
| 厂商： | HARRIS SEMICONDUCTOR |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | High Performance Microprocessor with Memory Management and Protection |
| 中文描述： | 16-BIT, 12.5 MHz, MICROPROCESSOR, CPGA68 |
| 文件页数： | 11/13页 |
| 文件大小： | 365K |
| 代理商： | IG80C286-12 |
3-138
80C286/883
NOTES:
1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
2. Address, M/IO and COD/lNTA may start floating during any T
C
depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in
φ
2 of T
C
.
3. BHE and LOCK may start floating after the end of any T
C
depending on when internal 80C286 bus arbiter decides to release bus to ex-
ternal HOLD. The float starts in
φ
1 of T
C
.
4. The minimum HOLD to HLDA time is shown. Maximum is one T
H
longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
Waveforms
(Continued)
VALID
VALID
VALID
(SEE NOTE 3)
(SEE NOTE 2)
(SEE NOTE 1)
(SEE NOTE 6)
(SEE NOTE 5)
NOT READY NOT READY
NOT READY NOT READY
(SEE NOTE 7)
READY
(SEE NOTE 7)
DELAY ENABLE
V
OH
T
H
φ
2
φ
1
T
H
φ
2
φ
1
T
H
φ
2
φ
1
BUS HOLD ACKNOWLEDGE
T
S
φ
2
φ
1
T
C
φ
2
φ
1
T
C
φ
2
φ
1
T
C
φ
2
φ
1
T
I
φ
2
φ
1
T
H
φ
2
φ
1
BUS HOLD
ACKNOWLEDGE
WRITE CYCLE
BUS CYCLE TYPE
CLK
HOLD
(SEE NOTE 4)
HLDA
S1
S0
A
23
- A
0
M/IO,
COD/INTA
D
15
- D
0
SRDY +
SRDYEN
ARDY +
ARDYEN
CMDLY
MWTC
DT/R
ALE
BHE, LOCK
DEN
8
8
8
TS - STATUS CYCLE
CT - COMMAND CYCLE
(SEE NOTE 1)
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