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参数资料
| 型号： | IMIC9716-ITB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | TSSOP-28 |
| 文件页数： | 6/12页 |
| 文件大小： | 108K |
| 代理商： | IMIC9716-ITB |
C9716-I
100 MHz Clock Generator with SSCG and Power Management for Mobile
Application
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev. 1.1
4/11/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Page 3 of 13
Frequency Selection Table
Outputs
Descriptions
48-24M/TS#
at Power UP
SEL
66/100
CPU
PCI
48M
48/24M
All Outputs Tri-State
0
Hi-Z
66 MHz
1
0
66.66 MHz
33.33 MHz
48 MHz
24/48 MHz
100 MHz
1
100.00 MHz
33.33 MHz
48 MHz
24/48 MHz
Test Mode
0
1
7.16 MHz
2.38 MHz
7.16 MHz
7.16/3.58 MHz
Power Management Functions
PS#
CS#
PD#
CPU
48M
PCI
PCI_F
VCOs
X
0
LOW
OFF
1
0
1
LOW
ON
0
1
X
ON
LOW
ON
CS# is an input clock synthesizer. It is used to turn off the CPU clocks for low power operation. CS# is asserted
asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock)
and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU
clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time
and CPU clock off latency needs to be 2 or 3 CPU clocks periods in time.
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