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参数资料
| 型号： | IMIC9716-ITB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | TSSOP-28 |
| 文件页数： | 7/12页 |
| 文件大小： | 108K |
| 代理商： | IMIC9716-ITB |
C9716-I
100 MHz Clock Generator with SSCG and Power Management for Mobile
Application
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev. 1.1
4/11/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Page 4 of 12
Power Management Timing
CPU
CS#
CPU STOP TIMING
CPU
PCI
REF
48M
PD#
POWER DOWN TIMING
PCI
PS#
PCI STOP TIMING
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running
after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior
to turning off the VCO’s and the Crystal. The power-up latency needs to be less than 3 mS. The power down latency
should be as short as possible but conforming to the sequence requirements shown below. AS# and CS# are
considered to be don’t cares during the power down operations.
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