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参数资料
| 型号： | IMIC9806CY |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 9/15页 |
| 文件大小： | 185K |
| 代理商： | IMIC9806CY |
C9806C
I
2C Frequency Clock Generator for Mobile Pentium II Applications.
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.0
2/9/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 3 of 15
http://www.imicorp.com
Power Management Functions
All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the low state.
All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.5
mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on
PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled
or disabled.
Pins 26 and 27 are inputs PCI_STOP# and CPU_STOP# respectively. A particular output is enabled only when both the
serial interface and these pins indicate that it should be enabled. The device clocks may be disabled according to the
following table in order to reduce power consumption. All clocks are stopped in the low state. All clocks maintain a valid
high period on transitions from running to stopped. On low to high transitions of PWR_DWN#, external circuitry should
allow 0.5 mS for the VCOs to stabilize prior to assuming the clock periods are correct. The CPU and PCI clocks
transition between running and stopped by waiting for one positive edge on PCICLK_F followed by a negative edge on
the clock of interest, after which high levels of the output are either enabled or disabled.
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPU*
PCI
OTHER CLKs
XTAL & VCOs
X
0
LOW
OFF
0
1
LOW
RUNNING
0
1
LOW
Running
RUNNING
1
0
1
Running
LOW
RUNNING
1
Running
RUNNING
Table 3
*If Byte1, bit2 is programmed to a “0”, then CPU0 is not affected by CPU_STP#, and keeps running when CPU-STP# is
asserted low.
Power Management Timing
wait
Stop on next falling edge
1 PCI_F clock
Stop on next falling edge
1 CPU clock
wait
CPU(0:1)
CPU_STP#
PCI_F
PCI(0:5)
PCI_STP#
Fig.2
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相关代理商/技术参数 |
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| IMIC9806JBT | 制造商:Cypress Semiconductor 功能描述:Development Tools, Notebook, Intel Piii /Celeron 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| IMIC9812DYBD | 制造商:IMI 功能描述: |
| IMIC9827H | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Clocks and Buffers |
| IMIC9827JT | 制造商:Rochester Electronics LLC 功能描述:TIMING DEVICE - Tape and Reel |
| IMIC9827JTT | 制造商:Rochester Electronics LLC 功能描述:TIMING DEVICE - Bulk |
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