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参数资料
| 型号： | IMISC462AYB |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.209 INCH, SSOP-28 |
| 文件页数： | 2/7页 |
| 文件大小： | 61K |
| 代理商： | IMISC462AYB |
SC462
Green PC Power Management Clock Generator
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.0
8/15/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 2 of 7
PIN DESCRIPTION
PIN
No.
Pin
Name
Description
OSCin,
OSCout
These pins form an on-chip reference oscillator when connected to terminals of an
external parallel resonant crystal (nominally 14.318 Mhz). OSCin may also serve as input
for an externally generated reference signal.
S0, S1,
and S2
Standard frequency select input. These inputs control the high speed MCLK frequency
selection. S0-S2 inputs control the CPU clock frequencies. All these inputs have internal
pull-ups.
ST0, ST1
Doze frequency select inputs. These pins set the Doze frequency for MCLK outputs when
DOZE# goes low. Both inputs have internal pull-ups. Four Doze frequencies can be
programmed.
MCLK1,
MCLK2
Master clock outputs. Progrmmable output frequencies can be selected using S0-S2
inputs shown in Table 1. The MCLK1 frequency is half of the MCLK2 frequency.
DOZE#
DOZE control pin. When DOZE# is high, the clock chip operates in the standard mode.
When this pin goes low, output frequencies are switched to the frequencies programmed
by ST0-ST1 pin. Switching to 16/8/4 Mhz, DOZE frequencies occur smoothly to allow
tracking by 486 CPU internal PLL. Switching to 2/1/0 Mhz, DOZE frequencies occur
quickly, without glitches, to support static CPU’s and SMI operating modes. See timing
diagrams for description. This pin has an internal pull-up.
TS#
Tri-state control pin. When TS# pin is low, all outputs except Bout pins are tri-stated and
VCO’s are turned off. The oscillator continues to run. This pin has an internal pull-up.
Bin
On-chip buffer input. this pin has an internal pull-up.
Bout [1:4]
Buffer output pins of Bin. These buffers are capable to sink or source 12 ma. they be used
to buffer critical clock lines.
RESUME#
This output supports the stop clock state of S series processors. RESUME# goes low when
DOZE# goes low. It will stay low until after DOZE# goes high and the MCLK outputs lock
back to the original frequency selected by S0-S2. Igoes high 1 millisecond after MCLK
output has reached stable frequency.
24 Mhz
24 Mhz floppy drive clock output.
8 Mhz
8 Mhz clock output
REF14
14.31818 Mhz output. Buffered output of on-chip reference oscillator or externally
provided reference.
LF1, LF2
These are the phase detector outputs for the clock generators. They are single-ended, tri-
state outputs for use as loop error signal. A 0.1uF capacitor to ground should be
connected from each pin to form the loop filter.
VSS
Circuit ground
VDD
Positive power supply.
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