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参数资料
| 型号： | IMISC670DYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 文件页数： | 6/12页 |
| 文件大小： | 505K |
| 代理商： | IMISC670DYB |
SC670
I
2C Clock Generator for Pentium Notebook Designs.
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.4
6/20/97
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 3 of 12
POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or stopped via the 2-wire control interface. All clocks are stopped in the low state.
All clocks maintain a valid high period on transitions from running to stopped and on transitions from stopped to running
when the chip was not powered down. On power up, the VCOs will stabilize to the correct pulse widths within about 0.2
mS. The CPU, SDRAM, and PCI clocks transition between running and stopped by waiting for one positive edge on
PCICLK_F followed by a negative edge on the clock of interest, after which high levels of the output are either enabled
or disabled.
When MODE=0, pins 26 and 27 are inputs PCI_STOP# and CPU_STOP# respectively (when MODE=1, these functions
are not available). A particular output is enabled only when both the serial interface and these pins indicate that it should
be enabled.
The IMISC670 clocks may be disabled according to the following table in order to reduce power
consumption. All clocks are stopped in the low state. All clocks maintain a valid high period on transitions from running
to stopped. On low to high transitions of PWR_DWN#, external circuitry should allow 0.2 mS for the VCOs to stabilize
prior to assuming the clock periods are correct. The CPU and PCI clocks transition between running and stopped by
waiting for one positive edge on PCICLK_F followed by a negative edge on the clock of interest, after which high levels
of the output are either enabled or disabled.
CPU_STOP#
PCI_STOP#
PWR_DWN#
CPUCLK
PCICLK
OTHER CLKs
XTAL & VCOs
X
0
LOW
OFF
0
1
LOW
RUNNING
0
1
LOW
33/30 MHZ
RUNNING
1
0
1
66/60 MHZ
LOW
RUNNING
1
66/60 MHZ
33/30 MHZ
RUNNING
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
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