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参数资料
| 型号： | IMISC680EYB |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 7/8页 |
| 文件大小： | 94K |
| 代理商： | IMISC680EYB |
SC680E
I
2C System Clock Buffer
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev.1.7
2/17/2000
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Page 7 of 8
PCB layout Suggestion
Via to VDD Plane
Via to GND Plane
Void (cut) in power plane
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
C1
FB2
22uF
C12
C7
C11
C10
C9
C8
C2
C4
C5
C6
This is only a layout recommendation for best performance and lower EMI. the designer may choose a different
approach but C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, and C11 (all are 0.1 uf) should always be used and placed
as close to their VDD pins as is physically possible.
C3
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