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参数资料
| 型号： | IMISG577CYB |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 4/10页 |
| 文件大小： | 166K |
| 代理商： | IMISG577CYB |
SG577C
Low EMI Clock Generator for Pentium II Systems with Power
Management
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 2.0
8/12/98
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
Page 3 of 10
Outputs
Descriptions
CPU
PCI, PCIF
48 MHz
REF1:3
IOAPIC
Tri-State
Hi-Z
Test Mode
TCLK/2
TCLK/4
TCLK/2
TCLK
NOTE: TCLK is a test clock that is driven into the XTAL_IN input during test mode.
POWER MANAGEMENT FUNCTIONS
All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PSTOP and CSTOP input pins. All clocks
are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on
transitions from stopped to running when the chip was not powered down. On power up, (after bring PD from a low to
high state) the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, and PCI clocks transition
between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of
interest, after which high levels of the output are either enabled or disabled.
CSTOP
PSTOP
PD
CPUCLK
PCICLK
OTHER CLKs
XTAL & VCOs
X
0
LOW
OFF
0
1
LOW
RUNNING
0
1
LOW
RUNNING
1
0
1
RUNNING
LOW
RUNNING
1
RUNNING
POWER MANAGEMENT TIMING
PCICLK_F
PSTOP
PCICLK(0:5)
CSTOP
CPUCLK(0:3)
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