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参数资料
| 型号： | IN74LV164D |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Octal Bus Transceivers And Registers With 3-State Outputs 24-SOIC -40 to 85 |
| 中文描述： | 8位SERIAL-IN/PARALLEL-OUT移位寄存器 |
| 文件页数： | 1/6页 |
| 文件大小： | 45K |
| 代理商： | IN74LV164D |
TECHNICAL DATA
1
INTEGRAL
8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER
The IN74LV164 is a low-voltage Si-gate CMOS device and is pin
and function compatible with the IN74HC/HCT164.
The IN74LV164 is an 8-bit edge-triggered shift register with serial
data entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (DSA or DSB); either input can be
used as an active HIGH enable for data entry through the other input.
Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition
of the clock (CP) input and enters into Q
0
, which is the logical AND of
the two data inputs (DSA, DSB ) that existed one set-up time prior to the
rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs
and clears the register asynchronously, forcing all outputs LOW.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 1.2 to 5.5 V
Low Input Current: 1.0
μ
A, 0.1
μ
à at ò = 25
°
Output Current: 6 mA at V
CC
= 3.0 V; 12 mA at V
CC
= 4.5 V
High Noise Immunity Characteristic of CMOS Devices
IN74LV164
1
14
1
14
N SUFFIX
PLASTIC DIP
D SUFFIX
SO
ORDERING INFORMATION
IN74LV164N
IN74LV164D
IZ74LV164
T
A
= -40
°
to 125
°
C for all packages
Plastic DIP
SOIC
chip
LOGIC DIAGRAM
PIN 14=V
CC
PIN 7 = GND
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Outputs
MR
CP
DSA
DSB
Q0 Q1 ... Q7
L
X
X
X
L
L … L
H
L
L
L
Q0 ... Q6
H
L
H
L
Q0 ... Q6
H
H
L
L
Q0 ... Q6
H
H
H
H
Q0 ... Q6
H = high voltage level
L = low voltage level
X = don’t care
1
2
3
5
4
6
7
V
CC
Q7
14
13
12
11
10
8
9
GND
DSA
DSB
Q0
Q1
Q2
Q3
Q6
Q5
Q4
MR
CP
DSA
DSB
CP
SERIAL
DATA
INPUTS
PARALLEL
DATA
OUTPUTS
MR
Q0
Q4
Q2
Q6
Q1
Q5
Q3
Q7
1
2
8
9
2
10
5
12
4
11
6
13
DATA
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