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参数资料
| 型号： | IN74LV574 |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 元件分类： | DRAM |
| 英文描述： | Replaced by SN74ABT7819A : 512 x 18 x 2 bidirectional synchronous FIFO memory 80-QFP 0 to 70 |
| 中文描述： | 八路D型触发器;上升沿触发（3态） |
| 文件页数： | 1/8页 |
| 文件大小： | 194K |
| 代理商： | IN74LV574 |
TECHNICAL DATA
1
INTEGRAL
Octal D-type flip-flop;
positive edge-trigger (3-State)
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for oriented
applications. A clock (CP) and an output enable (OE) input are common
to all flip-flops. The eight flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements on the LOW-
to-HIGH CP transition. When OE is LOW, the contents of the eight flip-
flops are available at the outputs. When OE is HIGH, the outputs go to
the high impedance OFF-state. Operation of the OE input does not affect
the state of the flip-flops.
Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL IC
S
Supply voltage range: 1.0 to 5.5 V
Low input current: 1.0
μ
à; 0.1
μ
à at ò = 25
°
High Noise Immunity Characteristic of CMOS Devices
IN74LV574
N SUFFIX
PLASTIC DIP
DW SUFFIX
SO
1
20
1
20
ORDERING INFORMATION
IN74LV574N
IN74LV574DW
IZ74LV574
T
A
= -40
°
to 125
°
C for all packages
Plastic DIP
SOIC
chip
FUNCTION TABLE
Inputs
Output
Output
Enable
Clock
D
Q
L
H
H
L
L
L
L
L,H,
X
no
change
H
X
X
Z
H= high level
L = low level
X = don’t care
Z = high impedance
LOGIC DIAGRAM
PIN 20=V
CC
PIN 10 = GND
PIN ASSIGNMENT
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| IN74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger |
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