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参数资料
| 型号： | IN74LV74 |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 中文描述： | 带设置和复位功能的双D触发器；上升沿触发 |
| 文件页数： | 5/7页 |
| 文件大小： | 161K |
| 代理商： | IN74LV74 |
IN74LV74
5
INTEGRAL
TIMING REQUIREMENTS
(C
L
=50 pF, t
r
=t
f
=6.0 ns)
Test
V
CC
Guaranteed Limit
-40
°
C to 85
°
C
min
Symbol
Parameter
conditions
V
25
°
C
125
°
C
min
Unit
min
max
max
max
t
w
Pulse Width, Clock, Set or
Reset
V
I
= 0 V or V
CC
Figures 1,2,3
1.2
2.0
*
75
25
16
-
-
-
96
32
20
-
-
-
114
38
24
-
-
-
ns
t
su
Setup Time, Data to Clock V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
25
16
10
-
-
-
32
20
13
-
-
-
40
24
15
-
-
-
ns
t
rem
Removal Time, Set or
Reset to Clock
V
I
= 0 V or V
CC
Figures 2,3
1.2
2.0
*
18
9
6
-
-
-
24
12
8
-
-
-
30
15
9
-
-
-
ns
t
h
Hold Time, Clock to Data
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
*
3
3
3
-
-
-
5
3
3
-
-
-
5
3
3
-
-
-
ns
f
c
Clock Frequency
V
I
= 0 V or V
CC
Figures 1,3
1.2
2.0
3.0
8
18
30
-
-
-
6
15
24
-
-
-
4
12
20
-
-
-
MHz
* V
CC
= 3.3
±
0.3 V
V
M
= 0.5
V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Figure 1. Switching Waveforms
相关PDF资料 |
PDF描述 |
|---|---|
| IN74LV74D | Dual D-type flip-flop with set and reset; positive-edge trigger |
| IN74LV74N | Dual D-type flip-flop with set and reset; positive-edge trigger |
| IN74LV86 | Quad 2-Input Exclusive OR Gate |
| IN74LV86D | Replaced by SN74ABT821A : 10-Bit Bus Interface Flip-Flops With 3-State Outputs 24-SSOP -40 to 85 |
| IN74LV86N | Replaced by SN74ABT821A : 10-Bit Bus Interface Flip-Flops With 3-State Outputs 24-SOIC -40 to 85 |
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