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参数资料
| 型号： | IN74LV74D |
| 厂商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual D-type flip-flop with set and reset; positive-edge trigger |
| 中文描述： | 带设置和复位功能的双D触发器；上升沿触发 |
| 文件页数： | 7/7页 |
| 文件大小： | 161K |
| 代理商： | IN74LV74D |
IN74LV74
7
INTEGRAL
CHIP PAD DIAGRAM
Location of marking (mm):
left lower corner x=0.520, y=0.865.
Chip thickness:
0.46
±
0.02 mm.
PAD LOCATION
Location (left lower corner), mm
X
0.118
0.118
0.286
0.597
0.895
1.100
1.100
1.100
1.100
0.851
0.540
0.297
0.118
0.118
Pad No
Symbol
Y
Pad size, mm
01
02
03
04
05
06
07
08
09
10
11
12
13
14
Reset 1
Data 1
Clock 1
Set 1
Q 1
Q 1
GND
Q 2
Q 2
Set 2
Clock 2
Data 2
Reset 2
V
CC
0.436
0.125
0.125
0.125
0.125
0.125
0.423
0.721
0.930
0.949
0.949
0.949
0.830
0.604
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
0.108 x 0.108
Note: Pad location is given as per metallization layer
02
01
04
03
06
05
08
07
10
09
12
11
14
13
Chip marking
25LV74
(0,0)
X
Y
1.32 + 0.03
1
相关PDF资料 |
PDF描述 |
|---|---|
| IN74LV74N | Dual D-type flip-flop with set and reset; positive-edge trigger |
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| IN74LV86N | Replaced by SN74ABT821A : 10-Bit Bus Interface Flip-Flops With 3-State Outputs 24-SOIC -40 to 85 |
| IN74LVU04D | CERAMIC CHIP/MIL-PRF-55681 |
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