参数资料
型号: IP1827TRPBF
厂商: International Rectifier
文件页数: 17/39页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 25A LGA
标准包装: 2,000
系列: iPOWIR™
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.6 V ~ 12 V
输入电压: 1.5 V ~ 16 V
PWM 型: 电压模式
频率 - 开关: 225kHz ~ 1.65MHz
电流 - 输出: 25A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 17-LLGA
包装: 带卷 (TR)
供应商设备封装: 17-LGA(7.65x7.65)
Highly ? Integrated ? 25A Single ‐ input ? Voltage, ?
Synchronous ? Buck ? Regulator ?
iP1827
In ? applications ? where ? only ? local ? sensing ? is ? required ? for ?
0.7V
feedback, ? the ? remote ? voltage ? sensing ? pins ? of ? the ? iP1827 ?
Voso
0.6V
may ? be ? dedicated ? to ? sensing ? the ? output ? for ? power ? good ?
indication ? and ? overvoltage ? protection. ??
0
POWER ? GOOD ? OUTPUT ? AND ??
OVER ‐ VOLTAGE ? PROTECTION ?
The ? IC ? continually ? monitors ? the ? output ? voltage ? via ? output ?
of ? the ? remote ? sense ? amplifier ? (Voso ? pin). ? The ? Voso ? voltage ?
forms ? an ? input ? to ? a ? window ? comparator ? whose ? upper ? and ?
lower ? thresholds ? are ? 0.7V ? and ? 0.51V ? respectively. ? Hence, ?
the ? Power ? Good ? signal ? is ? flagged ? when ? the ? Voso ? pin ?
voltage ? is ? within ? PGood ? window, ? i.e., ? between ? 0.51V ? and ?
0.69V, ? as ? shown ? in ? Figure ? 12a. ? The ? PGood ? pin ? is ? open ? drain ?
and ? it ? needs ? to ? be ? externally ? pulled ? high. ? High ? state ?
HDrv
0
LDrv
0
SS
0
indicates ? that ? output ? is ? in ? regulation. ? Figure ? 12a ? also ? shows ?
the ? PGood ? timing ? diagram ? with ? a ? 256 ? cycle ? delay ? between ?
the ? Voso ? voltage ? entering ? within ? the ? thresholds ? defined ? by ?
the ? PGood ? window ? and ? PGood ? going ? high ?
PGood
0
Figure ? 12b: ? iP1827 ? Signal ? Timing ? for ? OVP ?
?
If ? the ? output ? voltage ? exceeds ? the ? over ? voltage ? threshold ?
0.7V, ? an ? over ? voltage ? trip ? signal ? is ? asserted; ? this ? will ? turn ?
off ? the ? high ? side ? driver ? and ? turn ? on ? the ? low ? side ? driver ? until ?
the ? Voso ? voltage ? drops ? below ? the ? 0.7V ? threshold. ? Both ?
drivers ? are ? then ? turned ? off ? until ? a ? reset ? is ? performed ? by ?
cycling ? Vcc ? (or ? PVcc/Enable) ? or ? until ? another ? OVP ? event ?
occurs ? turning ? on ? the ? low ? side ? driver ? again. ?
Figure ? 12b ? shows ? the ? response ? in ? over ‐ voltage ? condition. ?
0.8V
0.2V
SS
0
0.7V
BODY ? BRAKING TM ??
The ? Body ? Braking ? feature ? of ? the ? iP1827 ? allows ? improved ?
transient ? response ? to ? step ‐ down ? load ? transients. ? A ? severe ?
step ‐ down ? load ? transient ? would ? cause ? an ? overshoot ? in ? the ?
output ? voltage ? and ? drive ? the ? Comp ? pin ? voltage ? down ? until ?
control ? saturation ? occurs ? demanding ? 0% ? duty ? cycle, ? and ?
the ? PWM ? input ? to ? the ? Control ? FET ? driver ? is ? kept ? OFF. ? When ?
the ? first ? such ? skipped ? pulse ? occurs, ? the ? iP1827 ? enters ? the ?
Body ? Braking ? mode, ? wherein ? the ? Sync ? FET ? is ? also ? turned ?
OFF. ? The ? inductor ? current ? then ? decays ? by ? freewheeling ?
through ? the ? body ? diode ? of ? the ? Sync ? FET. ? Thus, ? with ? Body ?
Braking, ? the ? forward ? voltage ? drop ? of ? the ? body ? diode ?
provides ? an ? additional ? voltage ? to ? discharge ? the ? inductor ?
current ? faster ? to ? the ? light ? load ? value ? as ? shown ? in ? equations ?
4 ? and ? 5 ? below: ?
V ? V D
? ? o , without body braking
Voso
0
0.51V
di L
dt
di L
dt
? ? o , with body braking
V
L
L
(4)
(5)
?
PGD
0
where ? V D = ? forward ? voltage ? drop ? of ? the ? body ? diode ? of ? the ?
Sync ? FET. ?
256/Fs
256/Fs
?
Figure ? 12a: ? iP1827 ? Power ? Good ? Signal ? Timing ? Diagram ?
The ? Body ? Braking ? mechanism ? is ? kept ? OFF ? during ? pre ‐ bias ??
operation. ? Also, ? in ? the ? event ? of ? an ? extremely ? severe ? load ?
step ‐ down ? transient ? causing ? an ? OVP, ? the ? Body ? Brake ? is ?
overridden ? by ? the ? OVP ? latch, ? which ? turns ? on ? the ? Sync ? FET. ?
17
March ? 5, ? 2012 ??? | ??? V1.4 ?
97599
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