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参数资料
| 型号： | IP82C54Z |
| 厂商： | INTERSIL CORP |
| 元件分类： | XO, clock |
| 英文描述： | CMOS Programmable Intervel Timer |
| 中文描述： | 3 TIMER(S), PROGRAMMABLE TIMER, PDIP24 |
| 封装： | LEAD FREE, PLASTIC, MS-011AA, DIP-24 |
| 文件页数： | 13/22页 |
| 文件大小： | 395K |
| 代理商： | IP82C54Z |
13
82C54
MODE 2: RATE GENERATOR
This Mode functions like a divide-by-N counter. It is typically
used to generate a Real Time Clock Interrupt. OUT will
initially be high. When the initial count has decremented to 1,
OUT goes low for one CLK pulse. OUT then goes high
again, the Counter reloads the initial count and the process
is repeated. Mode 2 is periodic; the same sequence is
repeated indefinitely. For an initial count of N, the sequence
repeats every N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low during an output pulse, OUT is set high
immediately. A trigger reloads the Counter with the initial
count on the next CLK pulse; OUT goes low N CLK pulses
after the trigger. Thus the GATE input can be used to
synchronize the Counter.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. OUT goes low N CLK
pulses after the initial count is written. This allows the
Counter to be synchronized by software also.
Writing a new count while counting does not affect the current
counting sequence. If a trigger is received after writing a new
count but before the end of the current period, the Counter will
be loaded with the new count on the next CLK pulse and
counting will continue from the end of the current counting
cycle.
MODE 3: SQUARE WAVE MODE
Mode 3 is typically used for Baud rate generation. Mode 3 is
similar to Mode 2 except for the duty cycle of OUT. OUT will
initially be high. When half the initial count has expired, OUT
goes low for the remainder of the count. Mode 3 is periodic;
the sequence above is repeated indefinitely. An initial count
of N results in a square wave with a period of N CLK cycles.
GATE = 1 enables counting; GATE = 0 disables counting. If
GATE goes low while OUT is low, OUT is set high
immediately; no CLK pulse is required. A trigger reloads the
Counter with the initial count on the next CLK pulse. Thus
the GATE input can be used to synchronize the Counter.
After writing a Control Word and initial count, the Counter will
be loaded on the next CLK pulse. This allows the Counter to
be synchronized by software also.
Writing a new count while counting does not affect the
current counting sequence. If a trigger is received after
writing a new count but before the end of the current half-
cycle of the square wave, the Counter will be loaded with the
new count on the next CLK pulse and counting will continue
from the new count. Otherwise, the new count will be loaded
at the end of the current half-cycle.
N
N
N
N
0
2
0
1
0
3
0
2
0
1
0
3
0
3
N
N
N
N
0
2
0
2
0
3
0
2
0
1
0
3
0
3
N
N
N
N
0
3
0
2
0
1
0
5
0
4
0
3
0
4
WR
CLK
GATE
OUT
CW = 14
LSB = 3
WR
CLK
GATE
OUT
CW = 14
LSB = 3
WR
CLK
GATE
OUT
CW = 14
LSB = 4
LSB = 5
FIGURE 11. MODE 2
N
N
N
N
0
2
0
4
0
2
0
4
0
2
0
4
0
2
0
4
0
4
0
2
N
N
N
N
0
4
0
2
0
5
0
2
0
5
0
4
0
2
0
5
0
5
0
2
N
N
N
N
0
2
0
4
0
2
0
2
0
2
0
4
0
2
0
4
0
4
0
2
WR
CLK
GATE
OUT
CW = 16 LSB = 4
WR
CLK
GATE
OUT
WR
CLK
GATE
OUT
CW = 16 LSB = 5
CW = 16 LSB = 4
FIGURE 12. MODE 3
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