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参数资料
| 型号： | IPBH6N03LAG |
| 厂商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | OptiMOS㈢2 Power-Transistor |
| 中文描述： | 的OptiMOS㈢2功率晶体管 |
| 文件页数： | 2/9页 |
| 文件大小： | 289K |
| 代理商： | IPBH6N03LAG |
IPBH6N03LA G
Parameter
Symbol Conditions
Unit
min.
typ.
max.
Thermal characteristics
Thermal resistance, junction - case
R
thJC
-
-
2.1
K/W
SMD version, device on PCB
R
thJA
minimal footprint
-
-
62
6 cm
2
cooling area
5)
-
-
40
Electrical characteristics,
at
T
j
=25 °C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage
V
(BR)DSS
V
GS
=0 V,
I
D
=1 mA
25
-
-
V
Gate threshold voltage
V
GS(th)
V
DS
=
V
GS
,
I
D
=30 μA
1.2
1.6
2
Zero gate voltage drain current
I
DSS
V
DS
=25 V,
V
GS
=0 V,
T
j
=25 °C
-
0.1
1
μA
V
DS
=25 V,
V
GS
=0 V,
T
j
=125 °C
-
10
100
Gate-source leakage current
I
GSS
V
GS
=20 V,
V
DS
=0 V
-
10
100
nA
Drain-source on-state resistance
R
DS(on)
V
GS
=4.5 V,
I
D
=30 A
-
8.2
10.2
m
V
GS
=10 V,
I
D
=50 A
-
5.2
6.2
Gate resistance
R
G
-
1.3
-
Transconductance
g
fs
|
V
DS
|>2|
I
D
|
R
DS(on)max
,
I
D
=50 A
34
68
-
S
5
Diagrams are related to straight lead
versions.
5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm
2
(one layer, 70 μm thick) copper area for drain
connection. PCB is vertical in still air.
Values
2)
Current is limited by bondwire; with an
R
thJC
=2.1 K/W the chip is able to carry 80 A.
4)
T
j,max
=150 °C and duty cycle
D
<0.25 for
V
GS
<-5 V
3)
See figure 3
Rev. 1.2
page 2
2006-05-11
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