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参数资料
| 型号： | IQ80C32-25 |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| 文件页数： | 20/109页 |
| 文件大小： | 10824K |
| 代理商： | IQ80C32-25 |
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23
AT32UC3A
Figure 9-2.
The AVR32UC Pipeline
9.2.2
AVR32A Microarchitecture Compliance
AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-
geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers and return status registers. Instead, all this information is stored on the system
stack. This saves chip area at the expense of slower interrupt handling.
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to store the status register and return address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register and continue execution at the popped return address.
9.2.3
Java Support
AVR32UC does not provide Java hardware acceleration.
9.2.4
Memory protection
The MPU allows the user to check all memory accesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.
9.2.5
Unaligned reference handling
AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
IF
ID
ALU
MUL
Regfile
w rite
Prefetch unit
Decode unit
ALU unit
Multiply unit
Load-store
unit
LS
Regfile
Read
32058K
AVR32-01/12
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