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参数资料
| 型号： | IR2277STRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC CURRENT SENSE 0.2& 16SOIC |
| 标准包装： | 1,000 |
| 功能： | 电流感应 |
| 精确度： | ±0.2% |
| 输入电压： | 8 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
IR2277S/IR2177S (PbF)
1.4 Analog Output (OUT)
The analog output is internally buffered and capable
of driving capacitive loads ranging up to 50nF.
V RH and V RL set the dynamic range and gain of OUT
pin.
Additional circuitry to protect A/D converter input
against excessive voltage is not required.
Hereafter follow some definitions (see Figure 10
and following).
V RH
V RH +V RL
2
OUT
V RH + V RL
? V in
?
?
?
?
V in =V inp -V inm
Input referred analog offset (V aos ): It is
the input that gives an output that equals
OUT = (referred to V SS ).
2
? OUT
Gain: It is defined by the ratio G a = .
Linearity: It is defined by the maximum
V RL
V SS
V RH
V in
V aos (V pos if PO is measured
instead of OUT)
Figure 10: Input offset definition
OUT
difference between the ideal OUT/ V in curve
and the measured curve depurated of the
offset voltage and the gain error.
The analog output is also defined by some dynamic
OUT
characteristics (see figure 8):
? Slew Rate (SL OUT ). The maximum slope of
OUT measured in V/ μ s
? Settling time (t settl ). Time needed by the
V RL
V SS
G a
G id
V in
V in
analog output (OUT) to reach 90% of final
?
?
value.
Measure delay (MD). It is defined by the
time interval between the actual SYNC
edge and PO rising edge.
Step response (SR). Is the time needed by
V RH
Figure 11: Gain definition
OUT
Output to reach the final value after a step
of the input.
Is always within the following range:
Linearity
1
2 ? f SYNC
+ MD + t settl ≤ SROUT ≤
1
f SYNC
+ MD + t settl
G a
Error
V RL
V SS
G id
V in
Figure 12: Linearity error definition
13
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