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参数资料
| 型号： | IR2277STRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC CURRENT SENSE 0.2& 16SOIC |
| 标准包装： | 1,000 |
| 功能： | 电流感应 |
| 精确度： | ±0.2% |
| 输入电压： | 8 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
IR2277S/IR2177S (PbF)
This method has the advantage of being simple and
low cost but may force some limitations on duty-
cycle and on-time since they are limited by the
requirement to refresh the charge in the bootstrap
capacitor.
Proper capacitor choice can reduce drastically
these limitations.
Bootstrap capacitor sizing
Given the maximum admitted voltage drop for V BS ,
namely ? V BS , the influencing factors contributing to
V BS decrease are:
? Floating section quiescent current ( I QBS );
? Floating section leakage current ( I LK )
? Bootstrap diode leakage current ( I LK_DIODE );
? Charge required by the internal level shifters
( Q LS ); typical 20nC
? Bootstrap capacitor leakage current ( I LK_CAP );
? High side on time ( T HON ).
I LK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using
at least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).
Then we have:
Q TOT = Q LS + ( I QBS + + I LK + I LK _ DIODE + I LK _ CAP ) ? T HON
The minimum size of bootstrap capacitor is then:
high side freewheeling diode get forwarded
biased
I LOAD = 0; the IGBT is not loaded while being
on and V CE can be neglected
V BS = V CC ? V F
I LOAD > 0; the load current flows through the
freewheeling diode
V BS = V CC ? V F + V FP
In this case we have the highest value for V BS .
Turning on the high side IGBT, I LOAD flows into it
and V S is pulled up.
b) Bootstrap Resistor
A resistor (R boot ) is placed in series with the
bootstrap diode (see Figure 20) to limit the current
when the bootstrap capacitor is initially charged. We
suggest not exceeding some Ohms (typically 5,
maximum 10 Ohms) to avoid increasing the V BS
time-constant. The minimum on time for charging
the bootstrap capacitor or for refreshing its charge
must be verified against this time-constant.
c) Bootstrap Capacitor
For high T HON designs where an electrolytic tank
capacitor is used, its ESR must be considered. This
parasitic resistance develops a voltage divider with
R boot generating a voltage step on V BS at the first
charge of bootstrap capacitor. The voltage step and
the related speed (dV BS /dt) should be limited. As a
general rule, ESR should meet the following
C BOOT min =
Q TOT
? V BS
constraint:
ESR
ESR + R BOOT
? V CC ≤ 3 V
Some important considerations
a) Voltage ripple
There are three different cases making the
bootstrap circuit get conductive (see Figure 20)
I LOAD < 0; the load current flows in the low side
IGBT displaying relevant V CEon
V BS = V CC ? V F ? V CEon
In this case we have the lowest value for V BS .
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off the
Vs node is pushed up by the load current until the
18
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best
compromise, the first acting as fast charge tank for
the gate charge only and limiting the dV BS /dt by
reducing the equivalent resistance while the second
keeps the V BS voltage drop inside the desired ? V BS .
d) Bootstrap Diode
The diode must have a BV> 600V (or 1200V
depending on application) and a fast recovery time
(t rr < 100 ns) to minimize the amount of charge fed
back from the bootstrap capacitor to V CC supply.
www.irf.com
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