参数资料
型号: IR2520DSTRPBF
厂商: International Rectifier
文件页数: 7/17页
文件大小: 0K
描述: IC BALLAST CTLR 600V IC 8-SOIC
标准包装: 2,500
类型: 镇流器控制器
频率: 34 ~ 86 kHz
电流 - 电源: 10mA
电流 - 输出: 230mA
电源电压: 12.6 V ~ 15.4 V
工作温度: -25°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
IR2520D(S) & (PbF)
Functional Description
Under-voltage Lock-Out Mode
The under-voltage lock-out mode (UVLO) is defined as the
state the IR2520D is in when VCC is below the turn-on
threshold of the IC. The IR2520D UVLO is designed to main-
tain an ultra-low supply current (I QCCUV <80uA), and to
guarantee that the IR2520D is fully functional before the
high- and low-side output gate drivers are activated. The
VCC capacitor, CVCC, is charged by current through sup-
ply resistor, RSUPPLY, minus the start-up current drawn by
the IR2520D (Figure 1). This resistor is chosen to provide
sufficient current to supply the IR2520D from the DC bus.
Once the capacitor voltage on VCC reaches the start-up
threshold, V CCUV +, the IR2520D turns on and HO and LO
start oscillating. Capacitor CVCC should be large enough to
hold the voltage at VCC above the V CCUV + threshold for
one half-cycle of the line voltage or until the external auxil-
iary supply can maintain the required supply voltage and
current to the IC.
DCBUS(+)
RSUPPLY
DCP2
MHS
high-side driver is enabled. During UVLO mode, the high- and
low-side gate driver outputs, HO and LO, are both low and
pin VCO is pulled down to COM for resetting the starting
frequency to the maximum.
Frequency Sweep Mode
When VCC exceeds V CCUV + threshold, the IR2520D enters
frequency sweep mode. An internal current source (Figure
2) charges the external capacitor on pin VCO, CVCO, and
the voltage on pin VCO starts ramping up linearly. An addi-
tional quick-start current (I VCOQS ) is also connected to the
VCO pin and charges the VCO pin initially to 0.85V. When the
VCO voltage exceeds 0.85V, the quick-start current is then
disconnected internally and the VCO voltage continues to
charge up with the normal frequency sweep current source
(I VCOFS ) (Figure 3). This quick-start brings the VCO voltage
quickly to the internal range of the VCO. The frequency ramps
down towards the resonance frequency of the high-Q bal-
last output stage causing the lamp voltage and load current to
increase. The voltage on pin VCO continues to increase and
the frequency keeps decreasing until the lamp ignites. If the
lamp ignites successfully, the voltage on pin VCO continues
to increase until it internally limits at 6V (V VCO_MAX ). The
frequency stops decreasing and stays at the minimum fre-
quency as programmed by an external resistor, RFMIN, on
pin FMIN. The minimum frequency should be set below the
CVCC
RFMIN
VCC
COM
FMIN
VCO
1
2
3
4
Bootstrap
FET
Driver
15.6V
CLAMP
VCC
UVLO
High-
and
Low-
side
Driver
8
7
6
5
VB
HO
VS
LO
CBS
CSNUB
TO LOAD
high-Q resonance frequency of the ballast output stage to
ensure that the frequency ramps through resonance for lamp
ignition (Figure 4). The desired preheat time can be set by
adjusting the slope of the VCO ramp with the external capaci-
tor CVCO.
CVCO
MLS
DCBUS(+)
DCP1
RSUPPLY
DCP2
DCBUS(-)
LOAD RETURN
MHS
Fig. 1 Start-up circuitry
An internal bootstrap MOSFET between VCC and VB and
external supply capacitor, CBS, determine the supply volt-
age for the high-side driver circuitry. An external charge
CVCC
RFMIN
VCC
COM
FMIN
VCO
1
2
3
Bootstrap
FET
Driver
15.6V
CLAMP
VCO
High-
and
Low-
side
Driver
8
7
6
VB
HO
VS
LO
CBS
CSNUB
TO LOAD
pump circuit consisting of capacitor CSNUB and diodes DCP1
and DCP2, comprises the auxiliary supply voltage for the
CVCO
4
5
MLS
low-side driver circuitry. To guarantee that the high-side
supply is charged up before the first pulse on pin HO, the
first pulse from the output drivers comes from the LO pin.
LO may oscillate several times until VB-VS exceeds the
high-side UVLO rising threshold, V BSUV+ (9 Volts), and the
www.irf.com
DCP1
DCBUS(-) LOAD RETURN
Fig. 2 Frequency sweep circuitry mode circuitry
7
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