参数资料
型号: IR3081AMTRPBF
厂商: International Rectifier
文件页数: 17/39页
文件大小: 0K
描述: IC CTRLR XPHASE VR10.0 28MLPQ
标准包装: 1
系列: XPhase™
应用: 处理器
电流 - 电源: 11mA
电源电压: 9.5 V ~ 14 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 28-MLPQ
供应商设备封装: 28-MLPQ(5x5)
包装: 标准包装
产品目录页面: 1381 (CN2011-ZH PDF)
其它名称: IR3081AMPBFDKR
IR3081APBF
VCC
(12V)
ENABLE
3.735V
3.685V
8.9V
UVLO
SS/DEL
1.3V
VOUT
PWRGD
OCP THRESHOLD
IOUT
DELAY
START-UP
(ENABLE GATES
FAULT MODE)
NORMAL OPERATION
(VOUT CHANGES DUE TO LOAD OCP
AND VID CHANGES)
HICCUP OVER-CURRENT
PROTECTION
RE-START
AFTER
OCP
POWER-DOWN
(VCC GATES
FAULT MODE)
Figure 10. Operating Waveforms
Power Good Output
The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During
soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.71V. The
PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in
operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage
regulation within the design limits can logically be assured however, assuming no component failure in the system.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can
be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage.
System Reference Voltage (VBIAS)
The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp amplitude
tracks the VBIAS voltage, which should be used to program the Phase IC trip points to minimize phase delay errors.
Precondition of IIN during Soft Start
IIN pin is clamped during the early stage of soft start, which disables current sharing function in the phase ICs to
prevent PWM ramp from pulling too low. When V(SS/DEL)<0.7V, the precondition latch is set, and IIN is clamped
to ground through a 10k ? resistor. After V(SS/DEL) is 1.3V above V(FB), error amplifier output is released. When
V(EAOUT) jumps above 0.6V, the precondition latch is reset and the IIN clamp is removed. Normal current
sharing in the phase ICs then resumes.
Page 17 of 39
1/31 /05
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