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| 型号： | IR3081M |
| 厂商： | International Rectifier |
| 英文描述： | XPHASE VR 10.0 CONTROL IC |
| 中文描述： | XPHASE村10.0控制IC |
| 文件页数： | 7/20页 |
| 文件大小： | 396K |
| 代理商： | IR3081M |
IR3081
Page 7 of 20
9/1/03
Figure 1 – System Block Diagram
PWM Control Method
The PWM block diagram of the
XPhase
TM
architecture is shown in Figure 2. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used
for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the
slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change
with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change
due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current.
VOUT
GND
RVFB
SYSTEM
REFERENCE
VOLTAGE
VBIAS
+
-
VBIAS
REGULATOR
VDAC
BIASIN
PWMRMP
RPWMRMP
+
-
CPWMRMP
+
-
CLOCK
PULSE
GENERATOR
ENABLE
RAMP
DISCHARGE
CLAMP
DACIN
+
-
VOSNS+
VOSNS-
RAMPIN+
+
-
RAMPIN-
ISHARE
VOSNS-
RDRP
+
-
VDRP
IIN
SCOMP
CSCOMP
O% DUTY
CYCLE
COMPARATOR
VDAC
VDRP
AMP
IFB
+
-
+
-
+
-
GATEH
EAIN
GATEL
CSIN+
CSIN-
VPEAK
VVALLEY
RAMP GENERATOR
50%
DUTY
CYCLE
RMPOUT
+
-
RRAMP1
RRAMP2
CURRENT
SENSE
AMP
PWM
LATCH
DOMINANT
RESET
SHARE
ADJUST
ERROR
AMP
S
R
X34
ERROR
AMP
IROSC
RAMP
SLOPE
ADJUST
EAOUT
X
0.91
FB
CONTROL IC
COUT
+
-
20mV
10K
+
-
CPWMRMP
CSCOMP
RPWMRMP
+
-
+
-
+
-
+
-
10K
+
-
+
-
RRAMP1
CCS
RCS
RRAMP2
BIASIN
ISHARE
EAIN
RAMPIN-
RAMPIN+
SCOMP
PWMRMP
GATEH
CSIN+
CSIN-
DACIN
GATEL
VIN
PHASE IC
PHASE IC
SHARE
ADJUST
ERROR
AMP
CURRENT
SENSE
AMP
PWM
LATCH
DORESET
X34
R
S
20mV
CLOCK
PULSE
GENERATOR
RAMP
SLOPE
ADJUST
ENABLE
PWM
COMPARATOR
O% DUTY
CYCLE
COMPARATOR
SYSTEM
REFERENCE
VOLTAGE
RAMP
DISCHARGE
CLAMP
X
0.91
CCS
RCS
PWM
COMPARATOR
Figure 2 – PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external
resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of
approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the
Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS
reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator
waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle.
The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3 shows the
Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for
synchronization by swapping the RAMP + and – pins.
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