参数资料
型号: IR3081MPBF
厂商: International Rectifier
文件页数: 12/40页
文件大小: 0K
描述: IC PHASE CONTROLLER 28MLPQ
标准包装: 100
系列: XPhase™
应用: 处理器
电流 - 电源: 11mA
电源电压: 9.5 V ~ 14 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 28-MLPQ
供应商设备封装: 28-MLPQ(5x5)
包装: 剪切带 (CT)
IR3081PBF
The IR3081PBF can accept changes in the VID code while operating and vary the DAC voltage accordingly. The
sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the
oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between
VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the
VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and
converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output
voltage.
It is desirable to prevent negative inductor currents in response to a request for a lower VID code. Negative current
transforms the buck converter into a boost converter and transfers energy from the output capacitors back into the
input voltage. This energy can cause voltage spikes and damage the silver box or other components unless they
are specifically designed to handle it. Furthermore, power is wasted during the transfer of energy from the output
back to the input.
The IR3081PBF includes circuitry that turns off both control and synchronous MOSFETs in response to a lower VID
code so that the load current instead of the inductor discharges the output capacitors. A lower VID code is detected
by the VID step-down detect comparator which monitors the “fast” output of the DAC (plus 7mV for noise immunity)
compared to the “slow” output of the VDAC pin. If a dynamic VID step down is detected, the body brake latch is set
and the output of the error amplifier is pulled down to 75% of the DAC voltage by the VID body brake clamp. This
triggers the Body Braking TM function which turns off both high side and low side drivers in the phase ICs.
The converter’s output voltage needs to be monitored and compared to the VDAC voltage to determine when to
resume normal operation. Unfortunately, the voltage on the FB pin can be pulled down by its compensation network
during the sudden decrease in the Error Amplifier’s output voltage so an additional pin BBFB is provided. The BBFB
pin is connected to the converter output voltage and VDRP pin with resistors of the same value as on the FB pin
and therefore provides an un-corrupted representation of converter output voltage. The regulation detect
comparator compares the BBFB to the VDAC voltage and resets the body brake latch releasing the error amplifier’s
output and allowing normal operation to resume. Body Braking TM during a transition to a lower VID code can be
disabled by connecting the BBFB pin to ground.
800ns
BLANKING
VID = 11111X DETECT
VID5
VID0
VID1
VID2
VID INPUT
COMPARATORS
(1 OF 6
DIGITAL TO
ANALOG
CONVERTER
+
"FAST" VDAC
+
VDAC BUFFER
AMP
VID3
VID4
SHOWN)
+
-
ISOURCE
ISINK
"SLOW" VDAC
VDAC
VOSNS-
EAOUT
TO ERROR AMP
0.6V
-
VID DOWN
BB CLAMP
ENABLE
75%
7mV
VID STEP-DOWN
DETECT
-
BODY
BRAKE
S
1.7us
BLANKING
COMPARATOR
-
+
IBBFB
LATCH
R
REGULATION
BBFB
DETECT
COMPARATOR
IROSC (From Current Source Generator)
Figure 7. VID Control Block Diagram
Page 12 of 40
10/01 /04
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