参数资料
型号: IR3500MTRPBF
厂商: International Rectifier
英文描述: XPHASE3TM VR11.0 & AMD PVID CONTROL IC
中文描述: XPHASE3TM VR11.0
文件页数: 23/47页
文件大小: 778K
代理商: IR3500MTRPBF
IR3500
Page 23 of 47
June 12, 2007
VCCL Under Voltage Lockout (UVLO)
The IR3500 has no under voltage lockout for converter input voltage (VCC), but monitors the VCCL voltage instead,
which is used for the gate drivers of phase ICs and circuits in control IC and phase ICs. During power up, the fault
latch will be reset if VCCL is above 94% of the voltage set by resistor divider at VCCLFB pin. If VCCL voltage drops
below 86% of the set value, the fault latch will be set.
VID Fault Codes
VID codes of 0000000X and 1111111X for VR11, and 11111 for AMD 5-bit Opteron will set the fault latch and
disable the error amplifier. A 1.3us delay is provided to prevent a fault condition from occurring during Dynamic VID
changes. A VID FAULT condition is latched for VR 11 with boot voltage and can only be cleared by cycling power to
VCCL.
Voltage Regulator Ready (VRRDY)
The VRRDY pin is an open-collector output and should be pulled up to a voltage source through a resistor. After
soft start cycle is complete, the VRRDY remains high until the output voltage is within regulation and SS/DEL is
above 3.92V. The VRRDY pin becomes low if the fault latch, over voltage latch, open sense line latch, or open
daisy chain latch is set. A high level at the VRRDY pin indicates that the converter is in operation and has no fault,
but does not ensure the output voltage is within the specification. Output voltage regulation within the design limits
can logically be assured however, assuming no component failure in the system.
Open Voltage Loop Detection
The output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. If any
fault condition forces the error amplifier output above VCCL-1.08V for 8 switching cycles, the fault latch is set. The
fault latch can only be cleared by cycling power to VCCL.
Load Current Indicator Output
The VDRP pin voltage represents the average current of the converter plus the VDAC voltage. The load current
information can be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage.
Enable Input
For Intel VID codes, pulling the ENABLE pin below 0.8V sets the Fault Latch and a voltage above 0.85V enables
the soft start of the converter. For AMD VID codes, pulling the ENABLE pin below 1.14V sets the Fault Latch and a
voltage above 1.2V enables the soft start of the converter.
Thermal Monitoring (VRHOT)
A resistor divider including a thermistor at the HOTSET pin sets the VRHOT threshold. The thermistor is usually
placed at the temperature sensitive region of the converter, and is linearized by a series resistor. The IR3500
compares the HOTSET pin voltage with a reference voltage of 1.6V. The VRHOT pin is an open-collector output
and should be pulled up to a voltage source through a resistor. If the thermal trip point is reached the VRHOT
output drives low. The hysteresis of the VRHOT comparator is added to eliminate toggling of VRHOT output.
Over Voltage Protection (OVP)
The output over-voltage happens during normal operation if a high side MOSFET short occurs or if output voltage is
out of regulation. The over-voltage protection comparator monitors Vo pin voltage. If Vo pin voltage exceeds VDAC
by 130mV, as shown in Figure 14, IR3500 raises ROSC/OVP pin voltage to V(VCCL) - 1V, which sends over
voltage signal to system. The ROSC/OVP pin can also be connected to a thyrister in a crowbar circuit, which pulls
the converter input low in over voltage conditions. The over voltage condition also sets the over voltage fault latch,
which pulls error amplifier output low to turn off the converter output. At the same time IIN pin (ISHARE of phase
ICs) is pulled up to VCCL to communicate the over voltage condition to phase ICs, as shown in Figure 15. In each
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