参数资料
型号: IR3505ZMTRPBF
厂商: International Rectifier
文件页数: 7/20页
文件大小: 0K
描述: IC XPHASE3 CTLR 2.5A 16-MLPQ
标准包装: 1
系列: XPhase3™
应用: 处理器
电流 - 电源: 3mA
电源电压: 8 V ~ 16 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-MLPQ
供应商设备封装: 16-MLPQ(3x3)
包装: 标准包装
其它名称: IR3505ZMTRPBFDKR
IR3505Z
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhase TM architecture is shown in Figure 1. Feed-forward voltage mode control with
trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used for the
voltage control loop. Input voltage is sensed in phase ICs and feed-forward control is realized. The PWM ramp slope will
change with the input voltage and automatically compensate for changes in the input voltage. The input voltage can
change due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to
changes in load current.
CONTROL IC
GATE DRIVE
VOLTAGE
PHSOUT
VIN
PHASE IC
VCC
CLOCK GENERATOR
CLKOUT
CLKIN
CLK Q
D
VCCH
PHSOUT
PHSIN
PHSIN
PWM
1
2
1
2
RESET
DOMINANT
D Q
CLK Q
4
5
GATEH
SW
CBST
VOSNS+
VOUT
REMOTE SENSE
EAIN
COMPARATOR
ENABLE
-
+
PWM LATCH
VCCL
GATEL
COUT
GND
AMPLIFIER
VO
VID6
RAMP
DISCHARGE
BODY
BRAKING
COMPARATOR
PGND
VOSNS-
LDO AMPLIFIER
VDAC
CLAMP
ERROR
LGND
SHARE ADJUST
ERROR AMPLIFIER
AMPLIFIER
VDAC
EAOUT
RCOMP
ISHARE
3K
-
VID6
VID6
+
CURRENT
SENSE
AMPLIFIER
CSIN+
CCOMP1
RFB1
RFB
VID6
VID6 +
CCS
RCS
CCOMP
+
CSIN-
FB
RVSETPT
CFB
RDRP1
DACIN
PHSOUT
IVSETPT
IROSC
VDRP
AMP
VSETPT
VDRP
CDRP
RDRP
CLKIN
CLK Q
PHASE IC
VCC
D
IIN
PHSIN
1
2
1
RESET
DOMINANT
D Q
4
VCCH
GATEH
CBST
PWM
COMPARATOR
-
2
CLK Q
5
SW
EAIN
+
PWM LATCH
VCCL
ENABLE
VID6
RAMP
DISCHARGE
BODY
BRAKING
COMPARATOR
GATEL
PGND
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
CURRENT
ISHARE
3K
-
VID6
VID6
+
SENSE
AMPLIFIER
CSIN+
VID6
DACIN
VID6 +
+
CSIN-
CCS
RCS
Figure 1 PWM Block Diagram
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an
external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC.
During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the
feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 2 shows the
phase timing for a four phase converter. The switching frequency is set by the resistor ROSC. The clock frequency
equals the number of phase times the switching frequency.
Page 7 of 20
March 17, 2009
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