参数资料
型号: IR3506MTRPBF
厂商: International Rectifier
文件页数: 8/21页
文件大小: 0K
描述: IC CTRL XPHASE3 DDR 16-MLPQ
标准包装: 3,000
系列: XPhase3™
应用: 处理器
电流 - 电源: 10mA
电源电压: 4.75 V ~ 7.5 V
工作温度: 0°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-MLPQ
供应商设备封装: 16-MLPQ(3x3)
包装: 带卷 (TR)
IR3506
Frequency and Phase Timing Control
The oscillator is located in the Control IC and the system clock frequency is programmable from 250kHz to 9MHZ by an
external resistor. The control IC system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase
timing of the phase ICs is controlled by the daisy chain loop, where control IC phase clock output (PHSOUT) is
connected to the phase clock input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to
PHSIN of the second phase IC, etc. and PHSOUT of the last phase IC is connected back to PHSIN of the control IC.
During power up, the control IC sends out clock signals from both CLKOUT and PHSOUT pins and detects the
feedback at PHSIN pin to determine the phase number and monitor any fault in the daisy chain loop. Figure 2 shows the
phase timing for a four-phase converter. The switching frequency is set by the resistor ROSC as shown in Figure 9. The
clock frequency equals the number of phase times the switching frequency.
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 2: Four Phase Oscillator Waveforms
PWM Operation
The PWM comparator is located in the phase IC. Upon receiving the falling edge of a clock pulse, the PWM latch is sets
and the PWM ramp voltage begins to increase. In conjunction, the low side driver is turned off and the high side driver is
turned on after a non-overlap time. When the PWM ramp voltage exceeds the error amplifier’s output voltage, the PWM
latch is reset. This turns off the high side driver, turns on the low side driver after the non-overlap time, and activates the
ramp discharge clamp. The clamp drives the PWM ramp voltage to a level set by the share adjust amplifier until the next
clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go to a 100% duty cycle in response to a load step increase
with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input range of
the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This arrangement
guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It also favors
response to a load step decrease which is appropriate given the low output to input voltage ratio of most systems. The
inductor current will increase much more rapidly than decrease in response to load transients. An additional advantage
of this PWM modulator is that differences in ground or input voltage at the phases have no effect on operation since the
PWM ramps are referenced to VDAC.
Figure 3 depicts PWM operating waveforms under various conditions.
Page 8 of 21
V3.02
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