参数资料
| 型号： | IR3508MTRPBF |
| 厂商： | International Rectifier |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC XPHASE3 CTLR 20-MLPQ |
| 标准包装： | 3,000 |
| 系列： | XPhase3™ |
| 应用： | 处理器 |
| 电流 - 电源： | 4mA |
| 电源电压： | 8 V ~ 28 V |
| 工作温度： | 0°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-MLPQ |
| 供应商设备封装： | 20-MLPQ（4x4） |
| 包装： | 带卷 (TR) |
IR3508
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout; therefore, minimizing the noise coupled to the IC.
x Dedicate at least one middle layer for a ground plane, which is then split into signal ground plane (LGND) and
power ground plane (PGND).
x Separate analog bus (EAIN, DACIN, and IOUT) from digital bus (CLKIN, PSI, PHSIN, and PHSOUT) to reduce
the noise coupling.
x Connect PGND to LGND pins of each phase IC to the ground tab, which is tied to LGND and PGND planes
respectively through vias.
x Place current sense resistors and capacitors (R CS and C CS ) close to phase IC. Use Kelvin connection for the
inductor current sense wires, but separate the two wires by ground polygon. The wire from the inductor
terminal to CSIN- should not cross over the fast transition nodes, i.e., switching nodes, gate drive outputs, and
bootstrap nodes.
x Place the decoupling capacitors C VCC and C VCCL as close as possible to VCC and VCCL pins of the phase IC
respectively.
x Place the phase IC as close as possible to the MOSFETs to reduce the parasitic resistance and inductance of
the gate drive paths.
x Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET. Use
combination of different packages of ceramic capacitors.
x There are two switching power loops. One loop includes the input capacitors, top MOSFET, inductor, output
capacitors and the load; another loop consists of bottom MOSFET, inductor, output capacitors and the load.
Route the switching power paths using wide and short traces or polygons; use multiple vias for connections
between layers.
To Digital Bus
To Analog Bus
LGND
PLANE
To Gate
Drive
Voltage
To Bottom
MOSFET
NC
PHSOUT
CLKIN
PGND
GATEL
NC
EAIN
CSIN -
CSIN+
VCC
To VIN
PGND
PLANE
To Switching
Node
To Top
MOSFET
To LGND
Plane
Ground
Polygon
To Inductor Sense
Page 15 of 19
October 27, 2008
相关PDF资料 |
PDF描述 |
|---|---|
| IR3508ZMTRPBF | IC CTRL XPHASE3 20MLPQ |
| IR3510MPBF | IC XPHASE CONTROL 32-MLPQ |
| IR3513ZMTRPBF | IC CTRL XPHASE3 POL 32-MLPQ |
| IR3514MTRPBF | IC XPHASE3 CONTROL HYBRD 40-MLPQ |
| IR3521MTRPBF | IC CTRL XPHASE3 SVID 32-MLPQ |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IR3508Z | 制造商:IRF 制造商全称:International Rectifier 功能描述:XPHASE3TM PHASE IC |
| IR3508ZMPBF | 制造商:IRF 制造商全称:International Rectifier 功能描述:XPHASE3TM PHASE IC |
| IR3508ZMTRPBF | 功能描述:开关变换器、稳压器与控制器 XPHASE3 DDR VTT 7V 2A 3 Wire RoHS:否 制造商:Texas Instruments 输出电压:1.2 V to 10 V 输出电流:300 mA 输出功率: 输入电压:3 V to 17 V 开关频率:1 MHz 工作温度范围: 安装风格:SMD/SMT 封装 / 箱体:WSON-8 封装:Reel |
| IR3510 | 制造商:IRF 制造商全称:International Rectifier 功能描述:HOT-SWAP N+1 REDUNDANT XPHASETM CONTROL IC |
| IR3510MPBF | 功能描述:IC XPHASE CONTROL 32-MLPQ RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:XPhase™ 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
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