参数资料
型号: IR3622AMTRPbF
厂商: International Rectifier
英文描述: HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING
中文描述: 高频2相,单或双输出同步降压控制器,输出跟踪和排序
文件页数: 17/33页
文件大小: 690K
代理商: IR3622AMTRPBF
IR3622AMPbF
www.irf.com
Compensation
for
Current
Loop
(slave channel)
The
slave
error
amplifier
is
differential
transconductance
amplifier,
in
2-phase
configuration the main goal for the slave channel
feedback loop is to control the inductor current to
match the master channel inductor current as
well provides highest bandwidth and adequate
phase margin for overall stability. The following
analysis is valid for both using external current
sense resistors and using DCR of the inductor.
The transfer function of power stage is
expressed by:
Where:
V
in=Input voltage
L
2=Output inductor
V
osc=Oscillator Peak Voltage
As shown the G(s) is a function of inductor
current. The transfer function for compensation
network is given by equation (23), when using a
series RC circuit as shown in figure22.
The loop gain function is:
24
)
22
(
-
V
sL
V
s
I
s
G
osc
2
in
e
2
L
*
)
(
)
(
=
L2
L1
C2
R2
RS2
RS1
Ve
IL2
IL1
Fb2
E/A2
Comp2
Vp2
)
23
(
-
sC
R
sC
1
R
g
R
s
V
s
T
2
s
1
s
m
2
s
e
+
=
*
)
(
)
(
[
]
2
s
R
s
T
s
G
s
H
*
)
(
*
)
(
)
(
=
+
=
osc
2
in
2
s
1
s
m
2
s
V
sL
V
sC
C
sR
1
R
g
R
s
H
*
)
(
Select a zero frequency for current loop (F
o2) 1.2
times larger than zero cross frequency for
voltage loop (F
o1).
From (24), R2 can be expressed as:
V
in=13.2V
V
osc=1.25V
g
m=3000umoh
L
2=0.4uH
R
s1=DCR=0.930mOhm
F
o2=72kHz
This results to : R
2=6.14K
Select R
2=6.09K
The power stage of current loop has a dominant
pole (Fp) at frequency expressed by:
Where R
ds(on1) is the on-resistance of control
FET, R
ds(on2) is the on-resistance of synchronous
FET, R
L is the DCR of output inductance and D
is the duty cycle
R
eq=3.7mOhm
Set the zero of compensator at 10 times the
dominant pole frequency F
P, the compensator
capacitor, C2 can be expressed as:
C
2=1.8nF
All design should be tested for stability
to verify the calculated values.
1
O
2
O
F
25
1
F
*
%
.
)
24
(
-
1
V
L
F
2
V
R
g
F
H
osc
2
O
in
2
1
s
m
2
O
=
*
)
(
π
)
25
(
-
V
L
F
2
R
g
1
R
in
osc
2
O
1
s
m
2
*
π
=
L
2
R
F
2
eq
P
*
π
=
L
2
on
ds
1
on
ds
eq
R
D
1
R
D
R
+
+
=
)
(
*
)
(
)
(
z
2
P
z
F
R
2
1
C
F
10
F
*
π
=
Fig. 22: The Compensation network for current loop
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